Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-05-01
2004-11-30
Cuneo, Kamand (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S455000, C438S458000, C438S474000, C438S977000
Reexamination Certificate
active
06825532
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to gettering in a semiconductor device and, more particularly, to a process for forming a bonded semiconductor-on-insulator substrate containing a planar intrinsic gettering zone and to a semiconductor device and an integrated circuit formed on the bonded substrate.
BACKGROUND OF THE INVENTION
During integrated circuit manufacture and processing, a silicon wafer may be exposed to metallic contaminants such as iron, nickel, zinc, chromium, and the like that may ultimately degrade the final product yield, performance, or reliability. This contamination may occur through contact with stainless steel wafer handlers and tools, diffusion of metallic substances from heater coils or lamps in high temperature processing chambers, or sputter debris dislodging from plasma chamber walls.
Gettering is a term that refers generally to any mechanism by which contaminating impurities, typically transition metals, are removed from sensitive semiconductor device regions and entrapped in other relatively benign domains of the wafer. Gettering is described in Wolf and Tauber,
Silicon Processing in the VLSI Era
, Vol. 1, 1986, Lattice Press, pp 61-70.
Gettering typically proceeds in three steps: 1) release of a contaminating element from its originating stable state and locale in the wafer into solid solution in the semiconductor crystal lattice; 2) diffusion of the contaminant through the crystal away from sensitive device structures or areas where susceptible structures are ultimately to be formed; and 3) capture of the contaminants by extended defects such as dislocations or precipitates at a position far enough away from devices to avoid interference with their operation and stable enough to prevent future liberation or discharge into the wafer during ensuing thermal, chemical and plasma treatments.
There are two basic categories of gettering mechanisms: extrinsic, or external, and intrinsic, or internal. These categories are discussed in U.S. Pat. No. 4,608,096 to Hill, the disclosure of which is incorporated herein by reference.
Extrinsic gettering entails the use of external means (usually on the wafer back surface) to create damage or stress in the silicon lattice, leading to the creation of extended defects capable of mobile metal capture. Examples of extrinsic gettering approaches include: diffused backside phosphorus or arsenic doping to tie up nickel, gold, iron, copper, etc., and mechanical or physical backside wafer damage produced by abrasion, grooving, sandblasting, laser deformation, ion implantation, polysilicon deposition, etc.
Intrinsic gettering is typically accomplished by the localized capture of impurities at extended defects that exist within the bulk material of the silicon wafer, for example, a Czochralski grown monocrystalline wafer containing interstitial oxygen (5-25 ppma). Intrinsic gettering usually involves the supersaturation of a region or zone of the silicon wafer with oxygen that will separate from solid solution and form clusters of silicon dioxide during thermal treatment. The stresses resulting from the agglomerate clusters cause stacking faults and dislocation loops that are capable of trapping impurities. To be effective, the clusters must be formed in the bulk of the wafer away from active device sites. Oxygen levels above the precipitation threshold must therefore be avoided in regions where active devices will be later be formed and permanently reside.
Various approaches have been taken in the past to provide gettering regions in a bonded semiconductor-on insulator substrate. For example, in U.S. Pat. No. 5,063,113 to Wada, the disclosure of which is incorporated herein by reference, defects for gettering sites are induced in a semiconductor layer by thermal treatment. However the defects are distributed vertically throughout the layer, extending even to the exterior surface, where they may adversely affect bonding of the layer with other layers. In addition, grinding and polishing of the layer results in substantial loss of the gettering sites.
U.S. Pat. No. 5,229,305 to Baker, the disclosure of which is incorporated herein by reference, describes a method for implanting boron, argon, krypton or, preferably, oxygen ions into a polished surface of a semiconductor layer, followed by thermal treatment, to create gettering sites in the layer. The polished surface of the semiconductor layer is then bonded to a handle substrate. Baker does not show implanting silicon ions into the silicon substrate. To create a high density gettering zone, Baker requires a large implant dose. Such a dose of non-semiconductor ions would alter the electrical characteristics of the semiconductor substrate.
Commonly employed gettering techniques are inadequate for use with many desired semiconductor devices. For example, the formation of gettering sites by treatment of the back surface of a device is generally unsuited for application to semiconductor-on-insulator structures. Also, defects that provide gettering sites are often generated in an indiscriminate, scattered fashion throughout the wafer and may thus adversely affect the performance of a device subsequently formed in the wafer.
There is a need for a method for making a bonded semiconductor-on-insulator substrate for integrated circuits that includes a high quality semiconductor device wafer having a smooth surface to promote its bonding integrity to a handle wafer and containing a well-defined, restricted intrinsic gettering zone close to but not detrimentally overlapping sites of devices that are particularly susceptible to metal contamination. There is a further need for a semiconductor substrate whose electrical characteristics are substantially unchanged by the formation of a gettering zone therein. The present invention meets these needs.
SUMMARY OF THE INVENTION
The present invention is directed to a method for forming a bonded semiconductor-on-insulator substrate for the fabrication of semiconductor devices and integrated circuits. Into a surface of a wafer of a monocrystalline semiconductor material, ions of the semiconductor material are implanted to a selected depth in the wafer to form, adjacent to the surface, an amorphous layer of the semiconductor material. The layer of amorphous semiconductor material extends to a substantially planar zone disposed at substantially the selected depth and comprising the monocrystalline semiconductor material damaged by lattice defects, i.e., end-of-range implant damage. Undamaged material below the selected depth comprises a first layer of the monocrystalline semiconductor material.
The wafer is heated under conditions effective to convert the amorphous layer to a second layer of the monocrystalline semiconductor material and to coalesce the zone of damaged monocrystalline semiconductor material, thereby forming a substantially planar intrinsic gettering zone of substantially pure semiconductor material that includes active gettering sites disposed at substantially the selected depth.
An insulating bond layer on one surface of a handle wafer is bonded to the surface of the wafer to form a bonded semiconductor-on-insulator substrate comprising a handle wafer, an insulating bond layer, and a device wafer of monocrystalline semiconductor material. The device wafer includes a substantially planar intrinsic gettering zone comprising substantially pure semiconductor material and including active gettering sites.
Also in accordance with the present invention is a bonded semiconductor-on-insulator substrate that includes a wafer comprising two layers of a monocrystalline semiconductor material separated by a planar intrinsic gettering zone that comprises substantially pure semiconductor material and contains active gettering sites. Further in accordance with the invention is a semiconductor device or integrated circuit formed on the described substrate.
The bonded substrate of the present invention includes a narrowly restricted gettering zone located in near proximity to device regions, which increases the efficiency of conta
Linn Jack H.
Rouse George V.
Shlepr Michael G.
Speece William H.
Cuneo Kamand
Fogg and Associates LLC
Intersil America's Inc.
Lundberg Scott V.
Sarkar Asok Kumar
LandOfFree
Bonded substrate for an integrated circuit containing a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bonded substrate for an integrated circuit containing a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bonded substrate for an integrated circuit containing a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3315348