Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2003-01-31
2004-08-31
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S406000, C438S977000
Reexamination Certificate
active
06784071
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to increase hole mobility and immunity to short channel effect for the creation of CMOS devices.
(2) Description of the Prior Art
It is well known in the art that Integrated Circuit (IC) devices that are created over Semiconductor-On-Insulator (SOI) surfaces have significant performance advantages such as reduced parasitic capacitances, reduced power consumption, increased resistance against radiation, increased ability to operate at more elevated temperatures, operational capabilities at higher applied voltages, multi-layer device integration and, for CMOS devices, increased freedom from latch-up of the operational devices. It is common practice in the creation of SOI devices, whereby the semiconductor is the upper layer, to create active surface regions by creating isolation trenches through the semiconductor layer down to the isolation layer, whereby the sidewalls of such trenches are covered with an insulation material such as silicon dioxide, silicon nitride, silicon oxynitride, CVD oxide, and the like.
One of the methods that is applied in the semiconductor technology for the extension of the crystalline nature of the silicon substrate is to grow a layer of epitaxy over the surface of the silicon substrate. The epitaxial layer, comprised of silicon, can be formed by conventional deposition techniques of contacting the substrate with a flow of gas (e.g. silicon tetrachloride) at an elevated temperature, the epitaxial layer can for instance include a N-well region and a P-well region previously created in the surface of a silicon substrate. Such an epitaxial layer may advantageously be grown because it may provide lower impurity concentrations and may even be of a different semiconductor type as the wafer over which it is grown. Semiconductor devices are in this case created in the active layer of the stack, which is typically only about a micron thick.
One of the more serious drawbacks of the use of epitaxial layers is that such a layer typically adopts the crystalline structure of the substrate over which the layer is created. In most applications, the underlying substrate is a monocrystalline substrate having a particular crystallographic orientation, thus potentially causing a conflict between a desired crystallographic orientation of the epitaxial layer and the crystallographic orientation of the substrate over which the epitaxial layer is grown. Additionally, successful creation of an epitaxial layer over a surface requires extreme preparation of the conditions of cleanliness of this surface in order to avoid the occurrence of undesirable crystalline defects (such as “pipes” and “spikes”) in the interface between the overlying layers. These and other considerations, which become more of a problem for semiconductor devices of increased complexity and increased surface area over which the devices are created, leads to the requirement of creating overlying surfaces of a crystalline nature that can be used for the creation of semiconductor devices.
It is well known in the art that the creation of semiconductor devices conventionally starts with a monocrystalline silicon substrate having <
100
> plane orientation. Other plane orientations of the cubic crystals that form the silicon substrate, such as <
110
> and <
111
>, are also well known but are, for considerations of device performance and wafer dicing, less frequently used. The invention provides a method that makes available a bonded SOI wafer with a <
100
> layer for the creation of active devices and a <
110
> substrate layer for performance improvements.
U.S. Pat. No. 6,271,101 B1 (Fukunaga) shows a SOI bonding process that discusses crystal orientation.
U.S. Pat. No. 5,310,446 (Konishi et al.) discloses a SOI bond process that discusses different orientation crystals.
U.S. Pat. No. 6,159,824 (Henley et al.) shows another SOI bond process discussing different orientation crystals.
U.S. Pat. No. 5,272,104 (Schrantz et al.) shows a SOI bonding process.
Article titled: Effect of <
100
> Channel direction for high Performance SCE Immune pMOSFET with Less Than 0.15 &mgr;m gate Length, H. Sayama et al., IEDM 1999.
SUMMARY OF THE INVENTION
A principle objective of the invention is to provide a silicon crystalline structure that can be advantageously used for the creation of semiconductor devices therewith.
Another objective of the invention is to provide a silicon crystalline structure of which an upper layer can be advantageously used for the creation of semiconductor devices therein and of which a lower layer can be advantageously used for the dicing of the created semiconductor devices.
Yet another objective of the invention is to provide a silicon crystalline structure such that semiconductor devices of improved device performance can be created in the surface thereof.
A still further objective of the invention is to provide a combination of semiconductor substrates having different planes of crystallographic orientation.
In accordance with the objectives of the invention a new silicon structure is provided. Under a first embodiment of the invention, a first silicon substrate having a <
100
> crystallographic orientation is bonded to the surface of a second silicon substrate having a <
110
> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are aligned with each other. Under a first embodiment of the invention, a first silicon substrate having a <
100
> crystallographic orientation is bonded to the surface of a second silicon substrate having a <
110
> crystallographic orientation, the wafer alignment notch of the first and the second silicon substrates are not aligned with each other.
REFERENCES:
patent: 5272104 (1993-12-01), Schrantz et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5804495 (1998-09-01), Saito et al.
patent: 5869386 (1999-02-01), Hamajima et al.
patent: 6066513 (2000-05-01), Pogge et al.
patent: 6159824 (2000-12-01), Henley et al.
patent: 6271101 (2001-08-01), Fukunaga
patent: 6372609 (2002-04-01), Aga et al.
patent: 6387829 (2002-05-01), Usenko et al.
Barth, “Silicon Fusion Bonding for Fabrication of Sensors, Actuators and Microstructures”, Sensors and Actuators, A21-A23 (1990) 919-926.
Sayama et al. “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15&mgr;m Gate Length”, 1999 IEEE, IEDM99-657, 27.5.1-27.5.3.
Chan Yi-Ling
Chen Haur-Ywh
Hu Chenming
Yang Fu-Liang
Yang Kuo-Nan
Chaudhari Chandra
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
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