Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-05
2004-09-07
Fourson, George (Department: 2823)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S617000
Reexamination Certificate
active
06789235
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices. More specifically, the invention relates to the inspection of wire bonds for semiconductor devices.
BACKGROUND OF THE INVENTION
To facilitate discussion,
FIG. 1
is a schematic illustration of a wire bonding system
100
that may be used in the wire bonding process. A host server
102
is connected to an Ethernet network
104
. The Ethernet network
104
is connected to a first host PC
106
, a second host PC
108
, an Ethernet hub
110
, a third host PC
114
, and a fourth host PC
116
. A Behavioral-Based Equipment Models (B-BEM) adapter program
112
is run on the Autoline controller
126
, manufactured by ESEC of Switzerland. The B-BEM adapter program
112
acts like a driver on the Autoline controller
126
to control the wire bonders. The first host PC
106
is connected to a first wire bonder
120
, which is a stand alone wire bonder through an RS232 connection. The second host PC
108
is connected to a second wire bonder
122
, which is also a stand alone wire bonder through an RS232 connection. The Ethernet hub
110
is connected to the Ethernet network
104
, the Autoline controller
126
and a Xyplex server
124
, which is sold by iTouch Communications of Littleton, Mass. and the Autoline controller
126
. The Xyplex server
124
is connected to a third wire bonder
128
and a fourth wire bonder
130
through RS232 connections. The third and fourth wire bonders
128
,
130
are Autoline wire bonders. The host PC's are able to communicate to the wire bonders using SEMI Equipment Communication Stardard (SECS). Other WAN, LAN, and standalone system combinations using different protocols may be used to allow a PC to monitor the schedule and processing of a wire bonder.
The first and second host PC's
106
,
108
communicate with the first and second wire bonders
120
,
122
respectively directly through the RS232 connections. The third and fourth host PC's
114
,
116
sends messages to the third and fourth wire bonders
128
,
130
respectively through the Ethernet hub to the Autoline controller
126
, which gates the messages through the Ethernet hub to the Xyplex server
124
and then to the third and fourth wire bonders
128
,
130
. A reverse path is used by the third and fourth wire bonders
128
,
130
to send messages back to the third and fourth host PC's
114
,
116
, respectively.
The host PC's
106
,
108
,
114
,
116
are used to perform analysis for the wire bonders for performance checking and to control the wire bonders
120
,
122
,
128
,
130
and to provide lot management.
To provide instructions for wire bonding a semiconductor chip, a master recipe may first be created for the semiconductor chip. The master recipe specifies the location of each wire bond. Such specification may provide an (x,y) rectangular coordinate for each wire bond. This master recipe may be created and managed by team of qualified recipe administrators. The master recipe is copied to the wire bonders. Since the wire bonders may have an offset, the wire bonders must be “taught” to compensate for the offset when the bonders are placed in a teaching mode. The offset may be a combination of a translational and rotational shift. The teaching of a wire bonder causes the creation of a slave recipe, which is a combination of the master recipe and the offset particular to the individual wire bonder. Sometimes slave recipes for one wire bonder are used as a starting point recipe for another wire bonder.
In a wire bond process, with the rise of number of bonding wires and bonding diagram complexity, bond program verification after teaching becomes the more and more tedious and time-consuming job. Bond recipe, once created, might be distributed to and re-used on multiple wire bonders for bonding the same device. Human mistakes could be made on the bond position definition during the offset teaching when the original bond recipe is re-used on the other bonders. Subsequently any teaching related mistake could cause very heavy yield loss if the wrong recipe is used and the mistake remains unchecked.
Two traditional methods had been used before for ensuring the rightness of bond program. The first method is to stipulate second party verification procedure after each bond program offset teaching. The verification may be done manually based on the certified bonding diagram on the paper. Obviously this method is neither effective nor productive, in the sense that it still heavily relies on the human judgment and is also very time-consuming. The second method is to make use of the ‘limited teach function’ feature provided by the wire bond equipment itself. This approach is to restrict the change of bond positions within a pre-defined limited range area. A password may be used to protect the limit setting. This method again is ineffective in terms of the security control.
It would be desirable to provide an automated bond program verification method.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a method for checking a wire bonding recipe is provided. Generally, coordinate data of a master recipe is stored. Coordinate data of a slave recipe is stored. The coordinate data of the slave recipe is compared with coordinate data of the master recipe. An error signal is provided if a mismatch is found between the coordinate data of the slave recipe and the coordinate data of the master recipe.
The invention also provides a computer readable medium containing program instructions for checking a wire bonding recipe. The program contains computer readable code for storing coordinate data of a master recipe, computer readable code for storing coordinate data of a slave recipe, computer readable code for comparing the coordinate data of the slave recipe with coordinate data of the master recipe, and computer readable code for providing an error signal if a mismatch is found between the coordinate data of the slave recipe and the coordinate data of the master recipe.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
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Provisional Application No. 60/230,396, filed Sep. 6, 2000.
Heng Soo Yeow
Lim Tian Han
Lu Qin
Natarajan Gunasekaran
Ong Eng Seng
Beyer Weaver & Thomas LLP
Fourson George
National Semiconductor Corporation
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