Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
1994-12-07
2001-10-09
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S734000, C257S736000, C257S738000, C257S750000, C257S763000, C257S764000, C257S765000, C257S770000, C257S774000, C257S781000
Reexamination Certificate
active
06300688
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to bond pads.
BACKGROUND INFORMATION
FIG. 1
(Prior Art) is a cross-sectional diagram of a bond pad structure. A layer of metal is deposited on a layer of oxide
2
and the metal is formed into a first metal plate
1
. Metal plate
1
has a square shape when viewed from a top-down perspective. As illustrated, a semiconductor substrate
3
underlies oxide layer
2
. After formation of first metal plate
1
, a second layer of oxide
4
is deposited over the entire die. An opening is then formed in oxide layer
4
down to first metal plate
1
and a second layer of metal is deposited over the entire die. The second layer of metal is then formed into a second metal plate
5
which also has a square shape when viewed from a top-down perspective. The entire die is then covered with passivation
6
. An opening is then formed through passivation
6
in the pad area to expose an upper surface of second metal plate
5
. The second layer of oxide
4
of the bond pad structure is the layer of oxide which typically separates a first layer of metal routing leads from an overlying second layer of metal routing leads elsewhere on the die. First metal plate
1
may be connected to other circuitry elsewhere on the die via signal routing leads (not shown) formed of the same first layer of metal that the first metal plate
1
is formed. Similarly, second metal plate
5
may be connected to other circuitry via other signal routing leads (not shown) formed of the same second layer of metal that the second metal plate
5
is formed.
During packaging, one end
8
of a bond wire
7
is attached to the second metal plate
5
and the other end of the bond wire is attached to a lead frame (not shown). End
8
is called a bond ball. The die, bond wires, and lead frame are then encapsulated in plastic to form the integrated circuit package. As the plastic of the package cools it solidifies it shrinks. Because the bond wires (and the bond balls) are encapsulated in the shrinking plastic, the shrinkage of the plastic with respect to the die is manifest as a force on the bond balls inward toward the center of the die. A stress, indicated in
FIG. 1
by arrows A, is therefore induced in the bond pad structure. Plates
1
and
5
which are made of relatively soft metal satisfactorily transfer the stress from the bond ball
8
to the relatively rigid oxide layer
2
which in turn transfers the stress to the underlying rigid semiconductor substrate
3
.
FIG. 2
(Prior Art) is a cross-sectional diagram of a metal-to-metal amorphous silicon antifuse structure
9
and another bond pad structure. An amorphous silicon feature
10
of antifuse
9
, when unprogrammed, has a high resistance which leaves a first signal routing lead
11
formed of the first metal layer essentially electrically isolated from a second signal routing lead
12
formed of the second metal layer. Antifuse
9
can, however, be programmed to form a permanent low resistance electrical connection between the first signal routing lead
11
and the second signal routing lead
12
. Programming is accomplished by flowing a suitable programming current through the amorphous silicon feature
10
such that a conductive filament is formed through the amorphous silicon feature
10
thereby connecting the second routing lead
12
to a conductive tungsten plug
13
of the antifuse structure. An electrical connection is therefore formed from the first signal routing lead
11
, through the tungsten plug
13
, through the filament in the amorphous silicon feature
10
, and to the second routing lead
12
.
To make the amorphous silicon antifuse structure
9
, oxide
4
is deposited and then a via is formed through the oxide
4
down to the first signal routing lead
11
. Tungsten is then blanket chemical vapor deposited (CVD) over the entire surface of the die so that tungsten fills the via and makes contact with the first signal routing lead
11
. The CVD tungsten deposits on all surfaces so that the via fills from the bottom and sides. As the tungsten is deposited in the minimum sized via, the tungsten deposited on the sidewalls of the via meets and completely fills the via. Thus, as the tungsten deposition process continues, the tungsten deposits on top of the filled via resulting in a somewhat planar surface. The tungsten is then reactive ion etched (RIE) back to the upper surface of oxide
4
. The RIE etchback removes a layer of tungsten from the non-via area and from the via area. However, because the vertical thickness of the tungsten in the via area is much thicker due to the sidewall deposition, a plug of tungsten is left in the via. After tungsten etching, a chemical/mechanical polishing process is used to planarize an upper surface of oxide
4
and tungsten plug
13
. A layer of amorphous silicon is then deposited onto this planar surface and etched to form an oversized version of silicon feature
10
. A second metal layer is then deposited and formed into second signal routing lead
12
. The oversized amorphous silicon feature is then etched to form the stack of the second metal routing
12
and the amorphous silicon feature
10
.
Due to the tungsten deposition and etch process, it is generally not desirable to have a large via in oxide
4
. The tungsten deposited on the via sidewalls cannot meet in the center of a large via. A thin portion of tungsten will therefore be left in the center of the via. During tungsten etchback, the thin center portion of tungsten will be removed leaving only a tungsten stringer around the periphery of the large via. During chemical/mechanical polish, the tungsten stringer which is bounded by oxide only on one side has a tendency to lift off. Pieces of tungsten stringer may be dispersed over the surface of the die and become a defect problem.
Accordingly, a plurality of minimum feature size vias are formed in oxide layer
4
so that the resulting tungsten plugs (one of which is designated with reference numeral
14
in
FIG. 2
) in the vias will provide a good electrical connection between the first metal plate
1
and the second metal plate
5
but will not have portions which tend to lift off. The remaining oxide forms a mesh-like oxide structure
15
between the first and second metal plates
1
and
5
. Accordingly, a bond pad is formed on the same die with an amorphous silicon antifuse structure
9
having a minimum feature size tungsten plug
13
.
A problem, however, exists with the structure of FIG.
2
. When the structure is encapsulated in plastic, a stress A develops between bond ball
8
and oxide layer
2
. Although metal plates
1
and
5
can deform to relieve the stress, oxide mesh
15
is relatively rigid and does not deform. Consequently, stress may develop in rigid mesh
15
thereby causing cracks
16
to form in rigid mesh
15
. The packaged integrated circuit may therefore have to be discarded due to a physically impaired bond pad structure.
SUMMARY
In one embodiment, a lower conductive plate having a strip-like opening is used in a bond pad structure having conductive plugs coupling the lower conductive plate to an upper conductive plate. A volume of relatively rigid material filling a volume above the strip-like opening transfers stress from the upper conductive plate, through the strip-like opening, and to a foundation layer upon which the lower conductive plate is disposed. The bond pad structure can be fabricated using the same process steps used to fabricate amorphous silicon antifuse structures having conductive plugs.
REFERENCES:
patent: 5289036 (1994-02-01), Nishimoto
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5412250 (1995-05-01), Bruggs
patent: 5502337 (1996-03-01), Nozaki
Halbert Michael J.
Lee Eddie
MacPherson Alan H.
QuickLogic Corporation
Skjerven Morrill & MacPherson LLP
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