Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1998-12-18
2001-04-10
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S121000, C438S123000, C438S124000, C438S125000, C438S126000, C438S127000, C438S117000, C438S666000, C257S691000, C257S697000, C257S786000
Reexamination Certificate
active
06214638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit package.
2. Description of Related Art
Integrated circuits are typically enclosed by a package that is mounted to an external printed circuit board. The integrated circuit has a plurality of outer die pads that are connected to corresponding bond fingers of the package. The pads are typically connected to the fingers by wires that are attached with an automated bonding machine.
The bond fingers have a width that is larger than the diameter of the wires to compensate for tolerances in the package, the integrated circuit and the bonding process of the wires. The width of each bond finger is significantly larger than the wire diameter to provide relatively large manufacturing yields for the package. A reduction in the bond finger width typically lowers the yield rate of the package.
The power and digital signals (I/O) of the integrated circuit are limited by the number of die pads that can be constructed on the device. Generally speaking the I/O and power can be increased by either enlarging the size of the integrated circuit or decreasing the spacing between die pads. The spacing is commonly referred to as the pad pitch. Increasing the size of the IC may reduce the yield of the device. Reducing the pitch requires a corresponding reduction in bond finger width which may also reduce the yield of the package. It would be desirable to provide a package that has a relatively low pad pitch but a high package yield rate.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit package which has a staggered bond wire pattern that increases the bond finger width to pad pitch ratio of the package. The package includes a first bond shelf, a second bond shelf and a third bond shelf. Mounted to the package is an integrated circuit which has a plurality of die pads. The die pads are arranged in a pattern of groups, wherein each group has a first die pad that is adjacent to a second die pad, and a third die pad that is adjacent to the second die pad and a first die pad of an adjacent group. Bond wires connect the first die pads to the first bond shelf, the second die pads to the second bond shelf and the third die pads to the third bond shelf, so that each adjacent die pad is connected to a different bond shelf. The staggered bond pattern maximizes the bond finger width of the package.
REFERENCES:
patent: 5091772 (1992-02-01), Kohara et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5582242 (1996-12-01), Hamburgen et al.
patent: 5633785 (1997-05-01), Parker et al.
patent: 5726860 (1998-03-01), Mozdzen
patent: 5734559 (1998-03-01), Banerjee et al.
patent: 5811880 (1998-09-01), Banerjee et al.
patent: 60-33746 (1986-08-01), None
patent: 1-191433 (1989-08-01), None
patent: 3-283646 (1991-12-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Intle Corporation
Wilczewski Mary
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