Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
1998-10-07
2001-07-10
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S738000, C257S778000, C257S786000, C361S760000, C361S773000, C361S774000
Reexamination Certificate
active
06259163
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof. With the rapid advent of portable devices such as mobile phones and IC cards in recent years, and the resulting need for thinner, lighter, more compact resin-sealed semiconductor devices to be mounted in those devices, a great number of means to fulfill such need have been proposed in the prior art. In one such instance, a method for mounting a resin-sealed semiconductor device
101
at an external substrate
102
such as a printed circuit board, as illustrated in
FIG. 31
, is proposed.
In the resin-sealed semiconductor device
101
that achieves this mounting state, a mold portion
104
constituted by sealing a semiconductor chip is provided at a front surface of a substrate
103
constituted of an epoxy resin, ceramic or the like and solder balls
105
to function as solder bumps are bonded in advance at specific connecting areas at a rear surface of the substrate
103
. Then, the semiconductor device
101
in this state is placed on the external substrate
102
and the entire assembly is placed in an atmosphere at a temperature ranging approximately from
220
centigrade to
240
centigrade. Thus, the solder balls
105
are at least partially melted so that the semiconductor device
101
can be mounted at the external substrate
102
. Through this mounting method, electrical characteristics with a low capacity and low inductance are achieved.
To describe the structure of the resin-sealed semiconductor device
101
that achieves this mounting state in more detail, in reference to
FIG. 32
, a metal pattern
106
formed at a rear surface of the substrate
103
is covered with an insulating film
107
constituted of, for instance, a solder resist, except at a specific connecting area
106
a,
the connecting area
106
a
is set so that it lies flush with a front surface of the insulating film
107
and a surface of the connecting area
106
a
is flat. A solder ball
105
is bonded to the connecting area
106
a.
When mounting the semiconductor device
101
at the external substrate
102
, the solder ball
105
is aligned at a specific electrode portion
109
formed between insulating layers
108
and
108
and then the entire assembly is placed in a specific heated atmosphere in this state.
However, the following problem manifests with the semiconductor device
101
in the prior art structured as described above in a reliability test which is performed after it is mounted at the external substrate
102
. Namely, during the reliability test in which the semiconductor device is exposed to an atmosphere at room temperature or within the range of -65 centigrade to 150 centigrade, an electrical disconnection sometimes occurs at the solder balls
105
. This is considered to be caused by the difference between the coefficients of thermal expansion of the semiconductor device
101
constituted of the substrate
103
and the mold portion
104
and of the external substrate
102
at which the semiconductor device
101
is mounted, which causes the semiconductor device
101
to be stretched and to contract, as illustrated in
FIG. 33
, causing cracks
110
and
111
to be formed at a solder ball
105
, which, in turn, leads to degradation of the electrical characteristics and eventually to disconnection as these cracks
110
and
111
grow to link with each other.
In an examination of the positions at which the cracks
110
and
111
are formed, their patterns and their directions, conducted by the inventor of the present invention, cracks were found to form near the metal pattern
106
to extend in parallel to the metal pattern
106
in most instances. The inventor of the present invention conducted a similar experiment after essentially modifying the shape of the metal pattern connecting area which is bonded with the solder ball, and a great improvement was observed.
SUMMARY OF THE INVENTION
A first object of the present invention, which has been completed by addressing the problem of the semiconductor devices and the manufacturing method thereof in the prior art, is to provide a new and improved semiconductor device with which it is possible to reduce the number of cracks that are formed compared to the prior art and even when they are formed, they are formed and extend in a direction in which disconnection does not readily occur.
A second object of the present invention is to provide a method for manufacturing such a semiconductor device.
In order to achieve the first object of the present invention, in a first aspect of the present invention, a semiconductor device provided with a substrate having a semiconductor chip at a front surface thereof and a conductor pattern formed at a rear surface of the substrate, i.e., at the mounting surface, with the conductor pattern covered with an insulating film except at specific connecting areas and solder bumps bonded to the connecting areas, which is characterized in that the area of the conductor pattern outside the connecting areas covered by the insulating film inclines toward the substrate, is provided.
An examination conducted by the inventor of the present invention verified that with the area of the conductor pattern such as a metal pattern covered with the insulating film outside the connecting areas made to incline toward the substrate, the rate of cracking is reduced and that even when a crack is formed, it extends almost along the inclination, i.e., in a diagonal direction. These results are assumed to be attributable to the stress at the solder bumps such as solder balls occurring in a diagonal direction and being dispersed, caused by the difference between the coefficients of thermal expansion described earlier. Thus, with the rate of cracking reduced, degradation in the electrical characteristics can be prevented, and furthermore, even when a crack occurs, it extends in a diagonal direction and, consequently, disconnections are greatly reduced too.
In the semiconductor device achieving the advantages described above, the area of the conductor pattern covered by the insulating film outside the connecting areas can be formed so that it becomes gradually thinner, as well as inclining toward the substrate. Furthermore, the portions of the rear surface of the substrate that correspond to the connecting areas may be distended toward the solder bumps with the that conforms to the distended shape.
In addition, in order to achieve the object described above, in a second aspect of the present invention, a semiconductor device provided with a substrate having a semiconductor chip at a front surface thereof and a conductor pattern formed at a rear surface of the substrate with the conductor pattern covered with an insulating film except at specific connecting areas and solder bumps bonded to the connecting areas, which is characterized in that a stage is provided between the connecting areas and the area covered with the insulating film at the conductor pattern with the staged portion formed to have a tapered shape.
In the semiconductor device structured as described above, too, the stress at the solder bumps occurs in a diagonal direction and the stress is dispersed. As a result, the degree of degradation in the electrical characteristics and occurrences of disconnection caused by cracks formed at the solder bumps are greatly reduced.
Furthermore, in a third aspect of the present invention, a semiconductor device provided with a substrate having a semiconductor chip at a front surface thereof and a conductor pattern formed at a rear surface of the substrate with the conductor pattern covered with an insulating film except at specific connecting areas and solder bumps bonded to the connecting areas, which is characterized in that the connecting areas project out further toward the solder bumps relative to the insulating film.
With the structure in which the connecting areas which are to be bonded with the solder bumps project out further relative to the insulating film, as described above, i.e., a structure in which the c
Anzai Noritaka
Egawa Yoshimi
Ohuchi Shinji
Chambliss Alonzo
Chaudhuri Olik
Jones Volentine, L.L.C.
OKI Electric Industry Co., Ltd.
LandOfFree
Bond pad for stress releif between a substrate and an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bond pad for stress releif between a substrate and an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bond pad for stress releif between a substrate and an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2448938