Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-02-15
2001-02-13
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S614000, C438S652000, C438S666000
Reexamination Certificate
active
06187658
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to very large scale integrated (VLSI) circuit packaging techniques and structures.
DESCRIPTION OF THE RELATED ART
The flip chip package is the most space efficient package for very large scale integrated (VLSI) circuits. In a flip chip package, an integrated circuit (IC) device has a plurality of bond pads distributed over the face of the device in a rectangular array . These bond pads are used to connect the IC device to the electrical paths on a printed circuit board (PCB). A solder bump or ball is formed on each of the bond pads of the IC device. The IC device and the PCB are positioned so that the solder bumps or balls contact the electrical paths on the PCB, and the assembly is heated to reflow the solder, forming electrical and mechanical bonds between the IC device and the PCB.
During use, the bond pads of the flip chip package are subjected to thermally induced shear stresses far in excess of those encountered by devices formed by other bonding techniques, such as wire bonding. In the flip chip package, the metal of the bond pads is subjected to compressive forces when the IC device dissipates power in the form of heat. The metal in the bond pads may be extruded upward plastically, to form bumps. When the IC device is subsequently cooled, the metal is stressed, which may cause a delamination type failure.
As thinner line widths (for example, between 0.12 and 0.16 &mgr;m) are incorporated into the IC designs, dielectric materials (surrounding metal conductors on the device) having low dielectric constants (typically less than 3.0) are used to increase speed without introducing cross-talk between the circuit paths in the device. Materials having the desired low dielectric constants tend to be mechanically weaker than materials having higher dielectric constants, increasing the likelihood of failure due to shear stress between the bond pads and the solder connections.
In the prior art, (wire bonded) devices greater than 0.3 &mgr;m have been constructed beneath the electrode bond pads, by depositing a solid metal cushion pad in the metal layer below the bond pads.
A structure and method are desired for reducing the likelihood of failure in VLSI devices during bonding and thermal cycling is desired.
SUMMARY OF THE INVENTION
The present invention is a bond pad support structure located beneath a bond pad on an integrated circuit, including a first bond pad support layer at least partly located below the bond pad, the first bond pad support layer having a plurality of radial patterns with at least one space between the radial patterns; and a second bond pad support layer located on the first bond pad support layer and filling at least a portion of the space.
A method of forming a bond pad support structure in an integrated circuit having a bond pad, includes the steps of: forming a first bond pad support layer at least partly located below the bond pad, the first bond pad support layer comprising a plurality of radial patterns with at least one space therebetween; and forming a second bond pad support layer on the first bond pad support layer, so that the second bond pad support layer fills at least a portion of the space.
REFERENCES:
patent: 5053850 (1991-10-01), Baker et al.
patent: 5220199 (1993-06-01), Owada et al.
patent: 5426266 (1995-06-01), Brown et al.
patent: 5739587 (1998-04-01), Sato
patent: 5751065 (1998-05-01), Chittipeddi et al.
patent: 5929521 (1999-07-01), Wark et al.
patent: 5962921 (1999-10-01), Farnworth et al.
patent: 5996343 (1999-11-01), Chittipeddi et al.
patent: 08-111544 (1996-04-01), None
Chittipeddi Sailesh
Ryan Vivian
Duane Morris & Heckscher LLP
Koffs Steven E.
Lucent Technologies - Inc.
Picardat Kevin M.
LandOfFree
Bond pad for a flip chip package, and method of forming the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bond pad for a flip chip package, and method of forming the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bond pad for a flip chip package, and method of forming the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2611334