Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-05
2001-03-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S758000, C257S773000
Reexamination Certificate
active
06207547
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to integrated circuits having bond pads incorporated therein.
BACKGROUND OF THE INVENTION
Much attention is given to certain aspects of integrated circuit (IC) technology, such as the number or dimensions of the devices in the circuit and circuit processing speeds that can reach millions of instructions per second (MIPS). Clearly, progress in these areas has great appeal and is readily understood. However, there are other aspects of very large scale integrated (VLSI) circuit technology that are of significant importance. For example, integrated circuits must be electrically contacted to be of any use within a larger electrical circuit. The electrical circuit from the external pins of the integrated circuit package must be connected to the integrated circuit through bond pads that are generally located on the periphery of the integrated circuit. The bond pads, which are typically exposed at the microchip die level, provide the interconnectivity between the integrated circuits on the die and the electrical circuit in which the microchip will be installed. They are generally located on the periphery of the integrated circuit die. Bond pads are metal areas that are electrically connected to the devices within the integrated circuit through buffers and electrically conducting interconnects. While the bond pads are formed during the layering process, wires must ultimately be attached to the bond pads to connect to the external pins of the completed integrated circuit package. As a result of conventional bonding technology, as well as the physical size of the wires and the nature of the bond, the bond pads have relatively large dimensions as compared to device dimensions. Because of their size, the bond pads occupy a significant percentage of the chip surface. The area underneath the bond pads thus occupies a substantial fraction of the entire chip surface.
The electrical connection between the package and the bond pad requires physical integrity as well as high electrical conductivity. The conventional bonding process used to form the connection typically requires elevated temperatures and/or relatively high pressures to produce a good connection between the wire and the bond pad. With the bond pad typically located on top of a dielectric layer, the bonding conditions produce thermal and mechanical stresses in the dielectric. These stresses may cause defects in the dielectric that, in turn, result in large leakage currents through the dielectric between the bond pads and the underlying, electrically-conducting substrate. These leakage currents have traditionally precluded use of the substrate area under the bond pads for active devices, thereby decreasing the device packing fraction. The buffers are typically located on the periphery of the integrated circuit and between bond pads to avoid placement under the bond pads. Similarly, the spacing between bond pads must be increased to accommodate the buffers or other devices.
In the prior art, active circuitry has been successfully constructed in the lower layers of an integrated circuit under the bond pad footprint by depositing a simple metal cushion pad in the metal layer below the bond pad. This metal pad acts as a cushion, protecting the dielectric layers below it from the pressure and heat of the wire bonding process. However, as the technology advances toward even smaller device sizes, which may be on the order of 0.3 or even 0.25 micron, this metal pad loses its effectiveness. Examination of integrated circuits at the 0.3 micron device size, shows cracks in the dielectric in at least 50 percent of the samples. Therefore, it must be concluded that this technology has reached its practical limit at a 0.3 micron device size.
Accordingly, what is needed in the art is an improved method for providing a bond pad support structure that substantially reduces the risk of damage to the circuit structure during the bonding process and allows more efficient use of chip area.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise a dielectric material.
Thus, the present invention provides a unique bond pad a structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer. It is believed that the inter-structural cooperation between these two layers provides a graded composite support structure that acts as a differential force transducer to buffer internal and bonding stresses within an integrated circuit.
In another embodiment, the bond pad support structure further comprises a plurality of openings wherein each of the openings is formed in a geometric pattern in the first bond pad support layer. The first bond pad support layer, in an advantageous embodiment, is located immediately under the bond pad. However, it will be appreciated that the bond pad support layer may be located at other levels below the bond pad as well. In one aspect of this particular embodiment, the openings form a plurality of nested geometric patterns in the first bond pad support layer. These nested geometric patterns may take on a variety of geometric shapes. For example, they may be rectangular, hexagonal, octagonal or may even be free-form. In yet another aspect, the nested geometric patterns are concentric geometric patterns.
The dimensions of opening or the nested geometric patterns may also vary. In one embodiment, an outer one of the nested geometric patterns may be wider than an inner one of the nested geometric patterns. Additionally, the nested geometric patterns may be spaced apart by a distance that decreases from an inner one of the nested geometric patterns to an outer one of the nested geometric patterns. It is believed that these dimensions and spacing may be varied to accommodate differing stress requirements within a given integrated circuit design.
In yet another embodiment the nested geometric patterns are positioned under at least a portion of a footprint of the bond pad. Alternatively, the footprint of the bond pad is positioned over the nested geometric patterns or, the opening may be positioned under at least a portion of a footprint of the bond pad.
In another aspect, the present invention provides a method of fabricating a bond pad support structure in an integrated circuit having a bond pad located thereon. In one illustrative embodiment, the method comprises the steps of forming a first bond pad support layer below the bond pad, forming an opening in the first bond pad support layer, and forming a second bond pad support layer on the first bond pad support layer and at least partially into the opening to form a bond pad support surface over at least a portion of the opening.
In yet another aspect, the present invention provides an integrated circuit system. In one embodiment, the integrated circuit system comprises a bond pad having a footprint and located on the integrated circuit system and a bond pad support structure. In this particular embodiment, the bond pad structure includes a conductive metal layer that is located below the bond pad and that has a plurality of nested geometric patterned openings formed therein. The bond pad structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the nested geometr
Chittipeddi Sailesh
Ryan Vivian
Bowers Charles
Lucent Technologies - Inc.
Smoot Stephen W.
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