Body voltage controlled semiconductor integrated circuit

Details Body voltage controlled semiconductor integrated circuit Body voltage controlled semiconductor integrated circuit

1997-06-03

2001-05-01

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S219000, C327S534000

Reexamination Certificate

active

06225846

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit using MOS transistors, and particularly to a body voltage controlled semiconductor integrated circuit operating with body voltages of the MOS transistors being controlled.
2. Description of Related Art
FIG. 5
is a circuit diagram showing a conventional body voltage controlled semiconductor integrated circuit. In this figure, the reference numeral
11
designates a first inverter, and
12
designates a second inverter. The first inverter
11
includes a PMOS transistor P
11
and an NMOS transistor N
11
, in which their gates are interconnected, their drains are also interconnected, the body electrode and source electrode of the PMOS transistor P
11
are connected to a power supply E
11
, and the body electrode and source electrode of the NMOS transistor N
11
are connected to earth E.
The second inverter
12
includes a PMOS transistor P
12
and an NMOS transistor N
12
, in which their gates are interconnected, their drains are also interconnected, their gates are connected to the output terminal of the first inverter
11
as well as to the body electrodes of the PMOS transistor P
12
and NMOS transistor N
12
, the source electrode of the PMOS transistor P
12
is connected to a power supply E
12
, and the source electrode of the NMOS transistor N
12
is connected to the earth E. In addition, a link L
12
interconnecting the drains of the two transistors of the first inverter
11
is connected to a link L
13
interconnecting the gates of the two transistors of the second inverter
12
.
The reference symbol “in” designates an input terminal connected to a link L
11
interconnecting the gates of the PMOS transistor P
11
and NMOS transistor N
11
, “out” designates an output terminal connected to a link L
14
interconnecting the drains of the PMOS transistor P
12
and NMOS transistor N
12
constituting the second inverter
12
, and c designates a load capacitance. Besides, the reference character G designates a gate electrode, B designates a body electrode, D designates a drain electrode and S designates a source electrode.
Next, the operation will be described. When the input terminal “in” is placed at H (high), the NMOS transistor N
11
is turned on and the output of the first inverter
11
falls to L (low). Thus, the PMOS transistor P
12
in the second inverter
12
is turned on, and the electric charge in the load capacitance c is absorbed to the power supply so that the output terminal “out” becomes H.
In this circuit, the PMOS transistor P
11
has a characteristic as shown in FIG.
6
: Its threshold voltage decreases with a decrease in the body voltage applied to its body. In contrast with this, the NMOS transistor N
11
has a characteristic as shown in FIG.
7
: Its threshold voltage decreases with an increase in the body voltage applied to its body. As their threshold voltage decreases, their operation is quickened. Incidentally, a related art to the conventional circuit is disclosed in Japanese patent application laid-open No. 7-86917, or U.S. Pat. No. 5,552,723.
The conventional body voltage controlled semiconductor integrated circuit with such a structure has the following problem. If a voltage above 0.8 V (built-in voltage) is applied to the second inverter
12
including the PMOS transistor P
12
and NMOS transistor N
12
with their gate electrodes connected to their body electrodes, a parasitic bipolar transistor composed of semiconductor layers forming the drain, body and source is turned on, and thus the transistors must operate in their saturation domain, which will retard their operation. This presents a problem in that the power supply voltage must be limited to below 0.8 V when the gate electrodes are connected to the body electrodes as in the second inverter
12
. Furthermore, there is another problem that such a circuit is weak to external noise.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a body voltage controlled semiconductor integrated circuit usable at the supply voltage above the built-in voltage.
According to a first aspect of the present invention, there is provided a body voltage controlled semiconductor integrated circuit comprising: a first inverter including a first PMOS transistor, a first NMOS transistor, a first link interconnecting a gate electrode of the first PMOS transistor and a gate electrode of the first NMOS transistor, a second link interconnecting a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor; a second inverter including a second PMOS transistor, a second NMOS transistor, a third link interconnecting a gate electrode of the second PMOS transistor and a gate electrode of the second NMOS transistor, a fourth link interconnecting a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor; a voltage divider circuit including a third PMOS transistor, a third NMOS transistor, a fifth link interconnecting a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor, a sixth link interconnecting a gate electrode of the third PMOS transistor and a gate electrode of the third NMOS transistor, a fourth PMOS transistor which is connected between a body electrode and a source electrode of the third PMOS transistor, and which is always kept ON, a fourth NMOS transistor which is connected between a body electrode and a source electrode of the third NMOS transistor, and which is always kept ON, wherein the fifth link is connected with the second link and the third link, the source electrode of the third PMOS transistor is connected to a body electrode of the second PMOS transistor, and the source electrode of the third NMOS transistor is connected to a body electrode of the second NMOS transistor.
According to a second aspect of the present invention, there is provided a body voltage controlled semiconductor integrated circuit comprising: a first inverter including a first PMOS transistor, a first NMOS transistor, a first link interconnecting a gate electrode of the first PMOS transistor and a gate electrode of the first NMOS transistor, a second link interconnecting a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor; a second inverter including a second PMOS transistor, a second NMOS transistor, a third link interconnecting a gate electrode of the second PMOS transistor and a gate electrode of the second NMOS transistor, a fourth link interconnecting a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor; a voltage divider circuit including a third PMOS transistor with its body electrode and source electrode interconnected, a third NMOS transistor with its body electrode and source electrode interconnected, a fifth link interconnecting a drain electrode of the third PMOS transistor and a drain electrode of the third NMOS transistor, a sixth link interconnecting a gate electrode of the third PMOS transistor and a gate electrode of the third NMOS transistor, a fourth PMOS transistor which is connected to the body electrode of the third PMOS transistor, and which is always kept ON, a fourth NMOS transistor which is connected to the body electrode of the third NMOS transistor, and which is always kept ON, wherein the fifth link is connected with the second link and the third link, the source electrode of the third PMOS transistor is connected to a body electrode of the second PMOS transistor, and the source electrode of the third NMOS transistor is connected to a body electrode of the second NMOS transistor.
Here, the sixth link may be connected to the fourth link.
The body voltage controlled semiconductor integrated circuit may further comprise a third inverter with its input terminal connected to the second link and its output terminal connected to the sixth link.


REFERENCES:
patent: 3702990 (1972-11

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