Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-08-24
2001-06-26
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S545000
Reexamination Certificate
active
06252452
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to CMOS semiconductor devices in which bias voltages different from the power supply potential and ground potential are applied to the substrates.
In CMOS semiconductor devices, to reduce the power consumption while maintaining high-speed operation, integrated circuits are designed using field effect transistors with low threshold voltages and low supply voltages.
In some devices, to decrease the current in the stand-by state of the circuit, i.e., so-called leakage current, or to compensate for variations in the threshold voltages during the operation of the circuit, substrate bias voltages different from the power supply potential and ground potential are applied.
In such devices, the lines for applying the substrate or well potential are not connected to the power supply lines or the ground line. For this reason, during the power on sequence when the operation of the substrate potential control circuit is still unstable, latch-up could occur because the power supply voltage could become higher than the substrate potential. To prevent this, each substrate is connected with an appropriate potential until a predetermined time period from the onset of the power-on elapses.
However, when the device has a plurality of the supply voltages, latch-up occurs during the power-on process, as will be described later.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device capable of preventing latch-up during the power-on period.
According to the present invention, there provided a semiconductor device in which a plurality of elements each operating upon receiving one of at least two power supplies are formed on substrates, and the lines for applying potential to the substrates are separated into a first potential line and a second potential line in accordance with the conductivity types of the substrates, comprising a potential connection means which connect the first and second potential lines with the power supply potential highest in the power supplies or the ground potential, respectively, in accordance with the conductivity type of the substrates until a predetermined period elapses, including the period after one of the power supplies is turned on prior to any other supplies until all the remaining power supplies are turned on.
The potential connection means may comprise a substrate bias circuit, the substrate bias circuit may generate a first substrate bias voltage high than the power supply potential and a second substrate bias voltage lower than the ground potential, and the potential connection means may connect the substrates with the power supply potential highest in the power supplies and the ground potential in accordance with the conductivity types of the substrates until the predetermined period elapses, including the period after one of the power supplies is turned on prior to any other supplies until all the remaining power supplies are turned on, and apply one of the first substrate bias voltages and the second substrate bias voltage to the semiconductor substrates in accordance with the conductivity type of the substrate after the predetermined period elapses.
The power supplies may include first power supplies and a second power supply having a voltage higher than those of the first power supplies, the second power supply potential may be applied to the substrate bias circuit, and the predetermined period may include a period after the second power supply is turned on until the first power supplies are turned on.
The potential connection means may comprise a reset circuit for measuring the predetermined period, the reset circuit may comprise an oscillator for generating clocks, and a counter for counting the clocks and outputting a reset signal of a first level when the count value reaches a predetermined value, and the potential connection means may connect the substrate with one of the power supply potential highest in the power supplies and the ground potential in accordance with the conductivity type of the substrates while the reset signal from the counter is a second level after one of the power supplies is turned on prior to any other supplies, and apply one of the first substrate bias voltages and the second substrate bias voltage to the semiconductor substrates in accordance with the conductivity type of the substrates after the reset signal from the counter becomes the first level.
The oscillator may have an enable terminal, which outputs the clocks while the enable signal is at the second level, and stops the generation of the clocks when the enable signal changes to the first level.
The oscillator preferably comprises a ring oscillator in which an odd number of inverters with a Schmitt trigger function are connected.
According to the present invention, there also provided a semiconductor device comprising first conductive substrate on which a plurality of elements each connected to one of at least two power supplies are formed, and a second conductive substrate on which elements connected to a ground potential are formed, a substrate bias circuit for generating the first and second substrate bias voltages to be applied to the first conductive substrate and the second conductive substrate, respectively, a first switching element connected between the first conductive substrate and a first potential lines, a second switching element connected between the second conductive substrate and a second potential line, and a reset circuit for controlling the first and second switching elements such that, before a predetermined period elapses, including the period after one of the power supplies is turned on prior to any other supplies until all the remaining power supplies are turned on, the first conductive substrates are connected to the first potential lines to fix the first conductive substrate at a first potential and the second conductive substrates are connected to the second potential line to fix the second conductive substrate at a second potential, and after the predetermined period elapses, the first conductive substrates are disconnected from the first potential line and the second conductive substrate is disconnected from the second potential line to apply the first and second substrate bias voltages to the first conductive substrates and the second conductive substrate, respectively.
According to the present invention, there also provided a semiconductor device comprising n-type substrates on which a plurality of elements each connected to one of at least two power supplies are formed, and a p-type substrate on which elements connected to a ground potential are formed, a substrate bias circuit for generating first and second substrate bias voltages to be applied to the n-type substrates and the p-type substrate, respectively, first diodes having the anodes connected to first output terminals of the substrate bias circuit, which supplies the first substrate bias voltages, and the cathodes connected to the n-type substrates, a second diode having the cathode connected to a second output terminal of the substrate bias circuit, which supplies the second substrate bias voltage, and the anode connected to the p-type substrate, first PMOS transistors having sources and drains connected between a power supply line of a first power supply included in the power supplies and the n-type substrates, and the gate connected to the first output terminal, a first NMOS transistor having a source and a drain connected between the p-type substrate and the ground line, and the gate connected to the second output terminal, second NMOS transistors having drains and sources connected between the gates of the first PMOS transistors and the ground lines, a second PMOS transistor having the drain and the source connected between the gate of the first NMOS transistor and the power supply line, and a reset circuit for controlling gate voltages of the second NMOS transistors and the second PMOS transistor to control opera
Fujita Tetsuya
Hatori Fumitoshi
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Nguyen Linh
Tran Toan
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