Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-02
2002-03-05
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S348000, C257S336000, C257S344000, C257S408000
Reexamination Certificate
active
06353245
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to body-tied-to-source transistors and to methods for fabricating such devices.
BACKGROUND: SILICON-ON-INSULATOR
Because of fundamental limitations on bulk insulated gate field effect transistors (MOSFET), it is difficult to achieve significant further improvement by changing the dimensions. Therefore, MOSFETs can only be improved significantly by changing the basic operation of the transistor. One important area of development over the last several years has been the use of silicon-on-insulator (SOI) devices to improve performance of MOSFETs. In SOI structures, the active semiconductor regions lie on top of an insulator layer. Thus each device on the integrated chip is formed from a separate mass of silicon (or other semiconductor), and the separate masses of silicon are electrically isolated from each other. One advantage of using SOI structures is that the parasitic capacitances that exist in bulk devices can be significantly reduced. Other advantages of SOI include some unique properties that allow low-power and low-voltage operations to be improved, and also (in some applications) enhance resistance to radiation damage.
BACKGROUND: PARTIALLY DEPLETED SOI MOSFETS
The most common device to be developed using SOI materials is a “partially depleted” SOI device. This name comes from the fact that the devices are constructed in a semiconductor layer which is thick enough that the channel region will not be fully depleted through its full thickness when the device is off. The advantage of this kind of structure is that the device operation and the device design are very close to the operation and design of a bulk complementary MOS (CMOS) device. However, there are several significant differences.
One difference is the floating-substrate effect. In bulk transistors, electrical connection is easily made through the substrate to the body node of a MOS transistor. The relatively fixed bias of the body node provides for a stable threshold voltage relative to the drain-to-source voltage. Conventional SOI transistors have the body node, the undepleted volume within the body region underlying the gate electrode, electrically floating, as the body node is isolated from the substrate by the underlying insulator film. When sufficient drain-to-body bias is applied, impact ionization can generate electron-hole pairs near the drain. Because majority carriers travel to the body node while the minority carriers travel to the drain, the electron-hole pairs near the drain cause a voltage differential to build up between the body node and the source of the transistor. This voltage differential lowers the effective threshold voltage and increases the drain current.
Another problem the floating body node of the SOI transistor presents is a parasitic “back channel” transistor. The substrate acts as the gate and the insulator film underlying the transistor acts as the gate dielectric. This back channel provides for a drain-source leakage path along the body node near the interface with the insulator film. Additionally, the dielectrically isolated body node allows capacitive coupling between the body node and the gate, and diode coupling between the body node and the source and drain. These two phenomena act to bias the body node and thus affect the threshold voltage. Each of these factors can contribute to undesirable performance shifts in the transistor relative to design, as well as to increased instability of the transistor operating characteristics.
BACKGROUND: BODY TIED-TO-SOURCE SOI
One approach, and the most direct approach, to resolving the floating-substrate problem is to prevent the charge from forming by creating a direct contact on the substrate to the source contact of the transistor. This eliminates the floating-substrate charging, but it complicates the layout of the device.
Prior to 1993, SOI devices used only lightly doped shallow source drain implants to improve resistance to punchthrough as well as improve hot carrier liability. The body-tied-to-source method of Blake (U.S. Pat. No. 4,965,213) was perfectly suited to devices of this type. (See
FIG. 6
for a diagram of Blake's method applied to a transistor with lightly doped shallow source drain implants, but without halo implants.) However, after 1993, halo ion implants were added to SOI devices to further improve resistance to punchthrough. The prior art is not compatible with such devices. The method of Blake, if applied to these new structures, would result in a device (see
FIG. 5
) that would not tie the body to the source. This is because the halo implant
560
on the source side of the transistor that would result using Blake's method is n-type semiconductor material while the body node
570
of the transistor is p-type semiconductor material. The body-tie implant
520
is also p-type semiconductor material. Therefore, since the halo implant
560
between the body-tie
520
and the body-node
570
is a different conductivity type, no electrical connection is made between the body
570
and the source
516
of the transistor.
Therefore a new body-tied-to-source method is needed to alleviate breakdown problems in partially depleted silicon-on-oxide insulated-gate field effect transistors (PD-SOI MOSFETs).
Innovative Structures and Methods
The present application discloses a body-tied-to-source semiconductor-on-insulator insulated-gate field effect transistor where the body-tie diffusion, which is used for tying the body to the source, is located within a “cut-out” of the source diffusion, where the source diffusion is not symmetric with the drain diffusion. (In one sample embodiment, the body-tie diffusion is ohmically connected to the source diffusion by a surface silicide layer.) Preferably the body-tie diffusion is laterally separated from the gate corner by a gap which is wide enough to avoid any diffusion of dopants from the body-tie diffusion into the channel region. This gap receives the shallow (MDD) drain extension implant, but not the main (n+ or p+) source/drain implant. Conduction from the well-tie implant to the channel region can occur using the portion of the body which lies beneath the MDD diffusion; this portion of the body would be wholly or partially blocked if it were exposed to the main source/drain implant.
Advantages of the disclosed methods and structures, in various embodiments, include some or all of the following: reduced process complexity and cost; minimal parasitic capacitance with maximal drive current, without the need for developing new processes; and/or easy alignment of the deep source/ drain (S/D) mask; compatibility with SOI or TFT processes using halo implants.
REFERENCES:
patent: 4965213 (1990-10-01), Blake
patent: 5001528 (1991-03-01), Bahraman
patent: 5683918 (1997-11-01), Smith et al.
Prediction of ESD Protection Levels and Novel Protection Devices in Thin Film SOI Technology; Raha et al.; EOS/ESD Symposium 97; pp. 356-365, 1997.
An Approach to Analytical Modeling of Snapback in SOI Devices; Huang et al.; 1990 IEEE; pp. 15-16.
The Effect of Intrinsic Body Resistance on the Breakdown Characteristics of DBTS NFD SOI MOSFETs; Suh et al.; 1993 IEEE; pp. 68-69.
Premature Breakdown in Non-Fully Depleted SOI/MOSFETs with Body-Tied-To-Source Structure; Hwang et al.; 1991 IEEE; pp. 34-35.
Dynamic Effects in BTG/SOI MOSFETs and Circuits Due to Distributed Body Resistance; Workman et al.; Proceedings 1997 IEEE International SOI Conf., Oct. 97; pp. 28-29.
Single-Event Charge Enhancement in SOI Devices; 1990 IEEE; Massengill et al.; pp. 98-99.
Brady W. James
Hoel Carlton H.
Telecky, Jr. Frederik J.
Tran Minh Loan
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