Body capacitor for SOI memory description

Details Body capacitor for SOI memory description Body capacitor for SOI memory description

2007-06-19

2007-06-19

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S244000, C257S068000

Reexamination Certificate

active

11064730

ABSTRACT:
A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

REFERENCES:
patent: 6284594 (2001-09-01), Ju et al.
patent: 6300243 (2001-10-01), Thakur

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