Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2008-04-21
2011-10-04
Clark, S. V (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S701000
Reexamination Certificate
active
08030751
ABSTRACT:
A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. Redistribution elements including these features, as well as semiconductor device assemblies including the redistribution elements and assembly methods, are also disclosed.
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Form APO/SG/210—Australian Patent Office Search Report dated Jun. 2, 2009, four (4) pages.
Chong Chin Hui
Corisis David J.
Lee Choon Kuan
Clark S. V
Micro)n Technology, Inc.
TraskBritt
LandOfFree
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