Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-03-28
2006-03-28
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S204000, C711S206000, C711S210000, C712S016000
Reexamination Certificate
active
07020761
ABSTRACT:
Processing restrictions of a computing environment are filtered and blocked, in certain circumstances, such that processing continues despite the restrictions. One restriction includes an indication that address translation is prohibited, in response to a buffer miss. When a processing unit of the computing environment is met with this restriction, it performs a comparison of page indices, which indicates whether the address translation can continue. If address translation can continue, the restriction is ignored. The processing unit includes a processor or a pageable entity, as examples.
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Gaertner Ute
Heller Lisa C.
Pfeffer Erwin F.
Siegel Timothy J.
Wagar Bruce A.
Augspurger, Esq. Lynn L.
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Namazi Mehdi
Padmanabhan Mano
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