Blocked net buffer insertion

Details Blocked net buffer insertion Blocked net buffer insertion

2002-03-06

2003-09-02

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C701S209000, C714S726000, C257S265000

Reexamination Certificate

active

06615401

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit design. More particularly, this invention relates to a method and system for timing optimization during integrated circuit design.
BACKGROUND
Integrated circuits consist of a large number of electronic components having individual logic devices or groups of logic devices, which are formed on a substrate, typically a silicon wafer. The components, or cells, are typically grouped to reduce the size and increase the speed of the integrated circuit. Each cell has one or more pins that are connected by wires to one or more pins of other cells of the integrated circuit. The pins are structures that function as the input or output of a cell, and the wires are structures that function as the interconnections between cells. A net is a set of pins connected by a set of wires.
Placement of the components in optimum positions provides efficient layout of the components in the integrated circuit, and tends to reduce integrated circuit costs, signal delays, size, and the like. Because integrated circuits typically contain hundreds of thousands if not millions of components, the task of optimizing the placement of components on in integrated circuit is typically not practical without the aid of computerized layout tools.
Designers address timing issues associated with the propagation of signals from one cell to another. For the integrated circuit design to function properly, the numerous signals that are transmitted between cells of the net are typically synchronized. Thus, designers make allowance for the delays inherent in the components of the integrated circuit and the routing between the components. Thus, faster routes must be synchronized with slower routes for the integrated circuit to function properly.
In addition to ensuring that electrical and timing aspects of the integrated circuit design are attended to, the physical layout of an integrated circuit can also present rigorous problems for the designer to overcome. For example, design constraints having a high priority may place some components in certain areas of the integrated circuits, which components may later become effectual blockages to other components having design constraints with a low priority. Thus, the low priority components need to be rerouted around the high priority blockages. Such rerouting must also take in to consideration the timing issues discussed below.
There is a need, therefore, for a method of routing a net around blockages, especially large blockages, whereby the net is effectively rerouted and timing considerations are accounted for.
SUMMARY
The above and other needs are met by a method of determining a desired connection path between a pair of points of a net separated by one or more blockages which will avoid path delays and ramp time violations without placing buffers within any of the blockages.
In a preferred embodiment, the method includes the steps of identifying a constructed path between the pair of points of the net, identifying the distance between the pair of points corresponding to the constructed path and comparing the distance to an optimal distance value, calculating a middle point of the constructed path when the distance between the pair of points corresponding to the constructed path is greater than the optimal distance value, and determining if the middle point is covered by a blockage.
If the middle point is not covered by a blockage, the union of each path between the middle point and each of the points of the pair of points is identified as the desired connection path,
If the middle point is covered by a blockage, visible angles of the blockage are determined. Next, first and second paths extending between the points of the pair of points and passing through at least one of the determined visible angles of the blockage are determined. Penalties for the first and second paths are then determined and compared. The one of the first and second paths having the least penalties is then selected as the desired connection path.
In another aspect, a computer program having logic elements for accomplishing the foregoing steps is provided.


REFERENCES:
patent: 6006025 (1999-12-01), Cook et al.
patent: 6415427 (2002-07-01), Nitta et al.
patent: 6480991 (2002-11-01), Cho et al.
Aipert et al., “Steiner Tree Optimization for Buffers, Blockages and Bays”, Apr. 4, 2001, Computer_Aided Design of Integrated Circuits and Systems, IEEE Transactions vol.: 20 Issue, pp.; 556-562.*
Srinivasan et al., “Mole-a sea-of-gates detailed router”, Dec. 1990, Design Automation Conferenc, 1990, EDAC, Proceedings of the European, pp.: 446-450.

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