Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-03-11
1999-04-06
Pan, Daniel H.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
39520058, 39520072, 711133, G06F 1314, G06F 1338
Patent
active
058929185
ABSTRACT:
A parallel computer system and a block transfer method and computer program for use with the parallel computer system which includes at least one processing unit divided into a plurality of logical processing units and a connecting device which exchanges commands and acknowledgements with the processing unit. The connecting device edits into a single command or acknowledgement individual commands or acknowledgements to be sent to the logical processing units and sends the single command or acknowledgement to the processing unit. The single command or acknowledgement includes a header, a command or acknowledgement code, logical processing unit numbers and pieces of command or acknowledge information corresponding to the logical processing units. The processing unit divides the single command or acknowledge into the individual commands or acknowledgements for the logical processing units and notifies the latter of these commands or acknowledgements. The invention operates in a similar manner when sending commands or acknowledgements from the logical processing units to the connecting device.
REFERENCES:
patent: 4675840 (1987-06-01), Raymond et al.
patent: 5388266 (1995-02-01), Frey et al.
patent: 5570367 (1996-10-01), Ayanoglu et al.
patent: 5740465 (1998-04-01), Matsunami et al.
Isono Soichi
Maya Yuzuru
Ohtsuji Akira
Hitachi , Ltd.
Pan Daniel H.
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