Block symmetrization in a field programmable gate array

Details Block symmetrization in a field programmable gate array Block symmetrization in a field programmable gate array

2007-06-19

2007-06-19

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000

Reexamination Certificate

active

11056984

ABSTRACT:
An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.

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Lai, Yen-Tai, “Hierarchical Interconnection Structures for Field Programmable Gate Arrays”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, No. 2, pp. 186-196, Jun. 1997.

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