Block segmentation of configuration lines for fault tolerant pro

Details Block segmentation of configuration lines for fault tolerant pro Block segmentation of configuration lines for fault tolerant pro

1995-12-11

1998-02-24

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 40, H03K 19177

Patent

active

057214980

ABSTRACT:
A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.

REFERENCES:
patent: 4020469 (1977-04-01), Manning et al.
patent: 4855954 (1989-08-01), Turner et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5336951 (1994-08-01), Josephson et al.
patent: 5394031 (1995-02-01), Britton et al.
patent: 5493239 (1996-02-01), Zlotnick

Affiliated with

Also associated with

Rating

Block segmentation of configuration lines for fault tolerant pro does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Block segmentation of configuration lines for fault tolerant pro, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block segmentation of configuration lines for fault tolerant pro will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1877109