Block partitioned dynamic semiconductor memory device

Details Block partitioned dynamic semiconductor memory device Block partitioned dynamic semiconductor memory device

1988-06-24

1990-06-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

36518901, 36523001, G11C 1300

Patent

active

049348264

ABSTRACT:
A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

REFERENCES:
patent: 3737879 (1973-06-01), Greene et al.
Bill Johnston, "The 64-K RAM: Which Way to Refresh?", Electronics, Jan. 4, 1979: 145,147.

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