Block level routing architecture in a field programmable...

Details Block level routing architecture in a field programmable... Block level routing architecture in a field programmable...

2000-03-06

2003-05-20

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S041000, C326S047000, C326S101000

Reexamination Certificate

active

06567968

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a field programmable gate array (FPGA) architecture. More particularly, the present invention relates to structures for coupling routing resources to one another in an FPGA architecture.
2. The Background Art
In the FPGA art, both antifuse based programmable architectures and SRAM based reprogrammable architectures are well known. In an FPGA, the logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements. In a antifuse based device, the number of the programmable elements far exceeds the number of elements in an SRAM based device because the area required for an antifuse is much smaller than an SRAM bit. Despite this space disadvantage of an SRAM based device, SRAM based devices are implemented because they are reprogrammble, whereas an antifuse device is presently one-time programmable.
Due to the area required for an SRAM bit, a reprogrammble SRAM bit cannot be provided to connect routing resources to each other and the logic elements at every desired location. The selection of only a limited number of locations for connecting the routing resources with one another and the logic elements is termed “depopulation”. Because the capability to place and route a wide variety of circuits in an FPGA depends upon the availability of routing and logic resources, the selection of the locations at which the programmable elements should be made with great care.
Some of the difficulties faced in the place and route caused by depopulation may be alleviated by creating symmetries in the FPGA. For example, look-up tables (LUT) are often employed at the logic level in an SRAM based FPGA, because a LUT has perfect symmetry among its inputs. The need for greater symmetry in a reprogrammable FPGA architecture does not end with the use of look-up tables. It also extends to the manner in which routing resources are connected together and the manner in which routing resources are connected to the logic elements. Without a high degree of symmetry in the architecture, the SRAM memory bit depopulation makes the place and route of nets in an SRAM based FPGA difficult.
It is therefore an object of the present invention to provide structures for connecting the routing resources in an FPGA to one another to improve the symmetry in the FPGA architecture.
It is another object of the present invention to provide structures for connecting the routing resources to the logic resources in an FPGA to improve the symmetry in the FPGA architecture.
BRIEF DESCRIPTION OF THE INVENTION
The present invention is directed to aspects of a semi-hierarchical architecture in an FPGA having top, middle and low levels. The FPGA architecture has structures for connecting the routing resources in the FPGA to one another and to the logic resources to improve the symmetry of the FPGA architecture and thereby increase the place and routability of an FPGA.
The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. The width freeway routing channel in the rectangular array can be changed to accommodate different numbers of B16×16 tiles without disturbing the internal structure of the B16×16 tiles. The freeway routing channels can be extended in any combination of directions at each end by a freeway turn matrix (F-turn).
A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B
1
blocks. The B16×16 tile is a nesting of a B2×2 tile that includes a two by two array of four B
1
blocks. The B2×2 tiles are stepped into a four by four array of sixteen B
1
blocks in a B4×4 tile, and the B4×4 tiles are stepped into a eight by eight array of sixty-four B
1
blocks in a B8×8 tile. A B16×16 tile includes four B8×8 tiles.
The routing resources in the middle level of hierarchy are expressway routing channels M
1
, M
2
, and M
3
including groups of interconnect conductors. The expressway routing channels M
1
, M
2
, and M
3
are segmented, and between each of the segments in the expressway routing channels M
1
, M
2
, and M
3
are disposed extensions that can extend the expressway routing channel M
1
, M
2
, or M
3
an identical distance along the same direction. The segments of an M
3
expressway routing channel is extended at the boundary of a B16×16 tile where an expressway routing channel M
3
crosses a freeway routing channel by an F-tab, and otherwise by an M
3
extension.
At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors.
Each horizontal and vertical BC routing channel is coupled to an expressway tabs (E-tab) to provide access for each B
1
block to the vertical and horizontal expressway routing channels M
1
, M
2
, and M
3
, respectively. At the E-tabs, the signals provided on the BC routing channels can connect to any of the expressway routing channels M
1
, M
2
, or M
3
. Once a signal emanating from a B
1
block has been placed on an expressway routing channel M
1
, M
2
or M
3
and traversed a selected distance, an E-tab is employed to direct that signal onto a horizontal or vertical BC routing channel into a B
1
block at a selected distance from the B
1
block from which the signal originated.
Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Block (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Further, between adjacent B
1
blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.


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Lai et al. (“Hierarchical interconnection structures for field programmable gate arrays”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 5, No. 2, Jun. 1997, pp. 186-196).

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