Block address translation circuit using two-bit to four-bit enco

Details Block address translation circuit using two-bit to four-bit enco Block address translation circuit using two-bit to four-bit enco

1996-12-19

1999-05-25

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

G06F 1210

Patent

active

059078669

ABSTRACT:
An approach for determining whether a current address is within an address range in which both the starting address of the range and the size of the address range are determined by variable register contents. Whereas the information in the variable register contents is in binary format, the current address is in a 2B format. The present invention provides logic for translating the binary formatted information so that it can be compared to the 2B formatted current address.

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patent: 4922415 (1990-05-01), Hemdal
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5530822 (1996-06-01), Beavers et al.
patent: 5530824 (1996-06-01), Peng et al.
patent: 5764589 (1998-06-01), Lotfi
patent: 5778407 (1998-07-01), Glew et al.

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