Black box timing model for latch-based systems

Details Black box timing model for latch-based systems Black box timing model for latch-based systems

2001-11-08

2004-03-02

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06701498

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to computer-aided design of integrated circuits and, more particularly, to methods for verifying the timing behavior of digital circuits.
2. Description of the Related Art
The current processes for designing custom digital circuits often hampers further improvements in cost and speed. Manufacturing was once the pinch-point in the development of large, custom digital circuits. Today, however, sub-micron manufacturing technologies allow millions, or even tens of millions, of gates to be reliably manufactured on larger wafers. The bottleneck is now very often the design process itself. System designers, for example, are forced to make global tradeoffs when selecting and configuring logic and memory cores. These tradeoffs greatly affect both performance and cost of the final design. Once these global architectural decisions are made, a more detailed design process follows, where the design is mapped and performance, chip size, and power objectives are achieved. As designs shrink to accommodate ever more gates and features, design verification becomes a more complicated process and a more pressing concern.
Verification is performed in a hierarchical manner. Circuit designs are partitioned into hierarchical blocks. Groups of circuit designers are then responsible for the design and for the implementation of each block. Higher level blocks are designed at higher levels of abstraction. As the design process continues, lower level sub-blocks use lower levels of abstraction—logic level, then circuit level, then layout level—until an eventual manufacturing release. The design of each sub-block must be verified to ensure the performance targets of higher blocks, and the global circuit design, are achieved.
If a hierarchical block is a flop-based design, verification has been accurately implemented. Because each path within the block ends at a flop device, a timing model of the block is simply achieved. The timing model consists of one delay number for each output pin and one setup constraint number on each input pin. One caveat to this simple model, however, is purely combinational paths from inputs to outputs. Another caveat is that the “one number” for each pin is actually a table of numbers for different possible slews and loads.
Producing realistic timing abstracts for latch-based blocks, however, has encountered several problems. One problem has been a loss of information between hierarchical blocks. Because custom circuit designs have millions of gates, circuit designers want to maintain as much information as possible between each hierarchical block. Because, however, higher levels of blocks are abstract versions of sub-blocks, valuable and necessary information is currently lost in the hierarchical, abstract design process for latch-based designs. Circuit designers then attempt various “corrections” to compensate for the information lost in a sub-block analysis. These corrections, however, often introduce excessive pessimism in the next hierarchical level, thus thwarting the creation of a realistic timing abstract. Another problem has been a lack of data compression for latch paths. Current methods may require entirely revealing a latch path within a block. Designers, however, often cannot reveal each latch path during the abstract, hierarchical design process. Blocks are then treated as boundaries and time borrowing is not allowed into or out of the block.
There are still other problems when creating accurate timing models of latch-based systems. Because a latch path may be multiple latches deep, another problem is determining a worst case set-up and launch relative to clock points inside the block. A further problem is that latch paths often time borrow all the way through a block to an output pin, thus making output times dependent upon input arrival times.
There is, accordingly, a need in the art for methods that create realistic timing abstracts for latch-based blocks in a hierarchical design process, methods that lose as little information as possible between hierarchies, methods that are accurate without introducing excessive pessimism, and methods that are simple to use and quick to implement.
BRIEF SUMMARY OF THE INVENTION
The aforementioned problems are minimized by the present invention. The present invention describes methods of creating timing models for digital circuits. These methods allow hierarchical circuit blocks to be treated as “black boxes” for timing analysis purposes. Because the present invention treats a circuit block as a black box, designers do not need to reveal latch paths within the block. Designers, for example, do not have to know how many latches are in a path. Designers, in fact, need to know very little about the circuit contents of a block.
The present invention will reveal set-ups and delays for a new block. The methods of the present invention determine a delay statement for an output of a black box model of the digital circuit. The methods also determine an input set-up constraint for an input of the black box model. This input set-up constraint, however, is based upon the delay statement. Constraints on any output pins are thus based upon the calculated delay numbers. Any necessary input arrival times are then determined such that any internal constraints are met. The circuit block is thus characterized by the delay statements and the input set-up constraints. Details of latch paths within the block are not necessary when revealing these set-up constraints and delays.
The present invention thus creates accurate timing abstracts of latch-based blocks. Because the block is characterized by the delay statements and the input set-up constraints, little or no information is lost at higher levels. Circuit designers are now assured of greater accuracy at each level of design. Designers can also quickly analyze the timing of larger blocks with greater numbers of input and output pins. The improved accuracy offered by the present invention means circuit performance targets are achieved faster, late design changes are reduced, and circuit masks have higher confidences.


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