Bitstream decoding apparatus with reduced error correction proce

Details Bitstream decoding apparatus with reduced error correction proce Bitstream decoding apparatus with reduced error correction proce

1997-06-26

1999-12-21

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714786, 714 3, H03M 1300

Patent

active

060063521

ABSTRACT:
A decoding apparatus and a decoding method are capable of minimizing degradation of the quality of images and sounds when a synchronous signal error occurs. The decoding apparatus includes a frame counter for receiving a bit stream, a synchronous pattern detector, a data error check unit, a synchronous detector, and a frame error determination unit. A synchronous detection error occurrence signal produced by the synchronous detector is not output to an external error processing circuit but is directly transmitted to the frame error determination unit. Even when the timing of an output synchronous pattern detection signal from the synchronous pattern detector and the timing of an output frame position signal from the frame counter do not match each other and a frame synchronous abnormality occurs, if the data itself is normal then decoding processing is executed without performing any error correction processing.

REFERENCES:
patent: 4796243 (1989-01-01), Kato
patent: 5596603 (1997-01-01), Haupt et al.
patent: 5764658 (1998-06-01), Sekiguchi et al.
Patent Abstracts of Japan, vol. 010, No. 116 (P-452), Apr. 30, 1986 & JP 60 246065 A (Hitashi), Dec. 5, 1985.
A Study on Variable Length Frame Synchronization for Mobile Multimedia Communications, Nobuhiko Naka, Takashi Suzuki, Toshiro Kawahara, Toshio Miki.

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