Bitline shielding for thyristor-based memory

Details Bitline shielding for thyristor-based memory Bitline shielding for thyristor-based memory

2008-01-15

2008-01-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189020, C365S230040

Reexamination Certificate

active

07319622

ABSTRACT:
Method and apparatus for writing and reading information to and from a memory cell. For a read, a write path is used to electrically shield at least one adjacent bitline from a bitline associated with the memory cell to be read, and the memory cell is read while the at least one adjacent bitline is electrically shielded from the bitline associated with the memory cell being read. For a write, the write path is used to electrically shield at the least one adjacent bitline from a bitline associated with a memory cell to be written to; memory cells coupled to a wordline are read and buffered; and the memory cell is written to while the at least one adjacent bitline is electrically shielded from the writing to the memory cell.

REFERENCES:
patent: 5644545 (1997-07-01), Fisch
patent: 6236618 (2001-05-01), Roy
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6583452 (2003-06-01), Cho et al.
patent: 6611452 (2003-08-01), Han
patent: 6653174 (2003-11-01), Cho et al.
patent: 6653175 (2003-11-01), Nemati et al.
patent: 6666481 (2003-12-01), Horch et al.
patent: 6683330 (2004-01-01), Horch et al.
patent: 6686612 (2004-02-01), Horch et al.
patent: 6690038 (2004-02-01), Cho et al.
patent: 6690039 (2004-02-01), Nemati et al.
patent: 6703646 (2004-03-01), Nemati et al.
patent: 6721220 (2004-04-01), Yoon et al.
patent: 6727528 (2004-04-01), Robins et al.
patent: 6734815 (2004-05-01), Abdollahi-Alibeik et al.
patent: 6735113 (2004-05-01), Yoon et al.
patent: 6756612 (2004-06-01), Nemati et al.
patent: 6756838 (2004-06-01), Wu et al.
patent: 6767770 (2004-07-01), Horch et al.
patent: 6677271 (2004-08-01), Robins et al.
patent: 6778435 (2004-08-01), Han et al.
patent: 6781888 (2004-08-01), Horch et al.
patent: 6785169 (2004-08-01), Nemati et al.
patent: 6790713 (2004-09-01), Horch
patent: 6804162 (2004-10-01), Eldridge et al.
patent: 6815734 (2004-11-01), Horch et al.
patent: 6818482 (2004-11-01), Horch et al.
patent: 6819278 (2004-11-01), Abdollahi-Alibeik et al.
patent: 6828176 (2004-12-01), Nemati et al.
patent: 6828202 (2004-12-01), Horch
patent: 6835997 (2004-12-01), Horch et al.
patent: 6845037 (2005-01-01), Han
patent: 6872602 (2005-03-01), Nemati et al.
patent: 6885581 (2005-04-01), Nemati et al.
patent: 6888176 (2005-05-01), Horch et al.
patent: 6888177 (2005-05-01), Nemati et al.
patent: 6891205 (2005-05-01), Cho et al.
patent: 6891774 (2005-05-01), Abdollahi-Alibeik et al.
patent: 6901021 (2005-05-01), Horch et al.
patent: 6903987 (2005-06-01), Yoon et al.
patent: 6911680 (2005-06-01), Horch et al.
patent: 6913955 (2005-07-01), Horch et al.
patent: 6937085 (2005-08-01), Samaddar
patent: 6940772 (2005-09-01), Horch et al.
patent: 6944051 (2005-09-01), Lee et al.
patent: 6947349 (2005-09-01), Abdollahi-Alibeik et al.
patent: 6953953 (2005-10-01), Horch
patent: 6958931 (2005-10-01), Yoon et al.
patent: 6965129 (2005-11-01), Horch et al.
patent: 6975260 (2005-12-01), Abdollahi-Alibeik et al.
patent: 6979602 (2005-12-01), Horch et al.
patent: 6980457 (2005-12-01), Horch et al.
patent: 6998298 (2006-02-01), Horch
patent: 6998652 (2006-02-01), Horch et al.
patent: 7006398 (2006-02-01), Yoon et al.
patent: WO 02/082504 (2002-10-01), None
Nemati, F. et al., Fully Planar 0.562um2 T-RAM Cell in a 130 nm SOI CMOS logic technology for high-density high-performance SRAMs. IEDM Technical Digest, 2004, IEEE.

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