Bitline reference voltage circuit

Details Bitline reference voltage circuit Bitline reference voltage circuit

2003-01-16

2004-09-07

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S149000

Reexamination Certificate

active

06788590

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to integrated circuit memories. More particularly, the present invention relates to a bitline reference voltage circuit for use in an integrated circuit memory.
For non VCC/
2
BL precharged DRAMs, establishing a reliable reference voltage is difficult. A prior art reference voltage circuit
10
is shown in FIG.
1
.
Transistor M
1
and capacitor C
1
, as well as transistor M
2
and capacitor C
2
, are extra memory cells placed along BL (bit line) and BLB (bit line bar) and serve as reference cells. Lines XE and XO are extra wordlines referred to as “X even” and “X odd” or “dummy” wordlines. Line XE goes high and transfers a reference voltage to bitline BL when a regular wordline WL (not shown in
FIG. 1
) accesses a memory cell (not shown in
FIG. 1
) attached to the inverted bitline BLB. Wordline XO goes high when a regular wordline WL accesses a memory cell attached to bitline BL. After sensing and restoring, a memory cell high level and a memory cell low level divided by two needs to be stored onto both capacitors C
1
and C
2
. This is accomplished by turning on the second dummy wordline during the restore operation, then turning both dummy wordlines off, then activating the SH line to charge share the charge on capacitors C
1
and C
2
so that the proper reference voltage is achieved.
The problem with this prior art technique is the complicated timing sequence required and the use of the extra transistor M
3
with its connections to cell nodes N
1
and N
2
in each of the reference cells. These nodes N
1
and N
2
are buried strap connections that are difficult to access. Making contact to these nodes could alter the capacitance on nodes N
1
and N
2
so that the reference cells would no longer match the regular memory cells without this connection. Modifying nodes N
1
and N
2
in this way would also undesirably change the leakage current of the reference memory cells.
Another prior art reference circuit uses VCC precharged bitlines wherein charge is bled off of capacitors C
1
and C
2
using wordlines XE or XO to generate a mid-level reference voltage. This reference circuit has the problem of not accurately setting the reference voltage level and the timing for bleeding the charge off of the reference node is difficult to control.
What is desired is a further refinement in the circuit and manner of operation of a bitline reference voltage circuit so that an accurate reference voltage can be achieved with minimum circuit and timing complexity.
SUMMARY OF THE INVENTION
In a first embodiment, a bitline reference voltage circuit according to the present invention includes a first transistor having a current path coupled between a first bitline and an intermediate node, and a gate for receiving a first control signal, a second transistor having a current path coupled between a second bitline and the intermediate node, and a gate for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.
In a second embodiment, a bitline reference voltage circuit according to the present invention includes a first plurality of transistors having current paths respectively coupled between a first plurality of bitlines and an intermediate node, and a plurality of gates coupled together for receiving a first control signal, a second plurality of transistors having current paths respectively coupled between a second plurality of bitlines and the intermediate node, and a plurality of gates coupled together for receiving a second control signal, a third transistor having current path coupled between the intermediate node and a source of constant voltage, and a gate for receiving a third control signal, and a capacitor coupled between the intermediate node and the source of constant voltage.
In both embodiments, the size of the reference capacitor is approximately one-half the size of a memory cell capacitor in the memory array.


REFERENCES:
patent: 4669065 (1987-05-01), Ohsawa
patent: 6002617 (1999-12-01), Manning
patent: 6111803 (2000-08-01), Derner et al.

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