Bitline pull-up circuit for compensating leakage current

Details Bitline pull-up circuit for compensating leakage current Bitline pull-up circuit for compensating leakage current

2001-12-20

2002-12-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189080, C365S149000, C365S203000

Reexamination Certificate

active

06501687

ABSTRACT:

The present invention claims the benefit of Korean Patent Application No. P2000-79270 filed in Korea on Dec. 20, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bitline pull-up circuit in a semiconductor memory, and more particularly, to a bitline pull-up circuit for compensating a leakage current, in which the leakage current from a bitline is compensated for making a memory operable at a low voltage.
2. Discussion of the Related Art
In general, a precharge cycle is provided next to a read/write cycle in making access to a memory cell, for bringing levels of a bitline and a bitbarline, which become to have a great difference, to an equal level, for which a bitline pull-up circuit is employed. However, in a memory operative at a voltage below 1.5V, and processed by a technique that can process a line below 0.18 &mgr;m, though it is required to drop a threshold voltage Vth as far as possible, the threshold voltage Vth can not be dropped below a certain level because the leakage current from the bitline becomes too great if the threshold voltage Vth is dropped below the certain level.
That is, referring to
FIG. 1
, a related art bitline pull-up circuit is provided with an equalizing PMOS transistor Pe connected between one pair of bitline BL and the bitbarline {overscore (BL)}, and one pair of pull-up PMOS transistors Pp and PpB at opposite ends of the equalizing PMOS transistor each having one end with a power source voltage applied thereto, wherein each of the equalizing PMOS transistor Pe, and the one pair of pull-up PMOS transistors Pp and PpB has a gate having an external signal eqb or pub, applied thereto.
FIG. 3
illustrates waveforms of the signals eqb and pub. The foregoing related art bitline pull-up circuit receives the equalizing signal eqb and the pull-up signal pub as shown in
FIG. 3
during a precharge cycle period from an outside of the circuit, to drive the equalizing PMOS transistor Pe, the pull-up PMOS transistors Pp and Ppb, for carrying out equalizing and pulling up operation. In an ideal case where there is no leakage current, since a voltage difference between the bitline BL and the bitbarline {overscore (BL)} detected at a read cycle period before and after the pull-up and equalizing is great, the sense amplifier for sensing the bitline {overscore (BL)} and the bitbarline {overscore (BL)} is operative regularly.
However, in order to minimize power consumption, a voltage of a power source of a mobile station is dropped to the maximum, requiring to drop power source voltages of devices employed in the mobile station, too. The drop of the power source voltage requires a drop of the threshold voltage Vth of the device, that results in a greater leakage current of the device. Particularly, though a low power SRAM, operative at a voltage in a range of 1V, is required to drop the threshold voltage Vth to the maximum for smooth operation of the device, the threshold voltage of the SRAM can not be dropped to a desired level because the leakage current increases sharply when the threshold voltage reaches below a certain level.
The leakage current causes a serious problem in the bitline of the SRAM; if the leakage current from the bitline is great as shown in
FIG. 3
, a voltage difference V{overscore (BL)} between the bitlines BL and the bitbarline {overscore (BL)} is reduced, such that the sense amplifier requires a more time period for sensing the voltages of the bitline {overscore (BL)} and the bitbarline YL with a speed delay, to cause malfunction of the sense amplifier in a worst case, to cause a trouble of the device itself.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a bitline pull-up circuit for compensating a leakage current that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a bitline pull-up circuit for compensating a leakage current, in which the leakage from the bitline is compensated for preventing a speed delay caused by an increased sensing time period, or malfunction of a sense amplifier in driving a low power semiconductor memory.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a bitline pull-up circuit for compensating a leakage current includes one pair of bitline pull-up transistors, one bitline equalizing transistor, a leakage current sensing part having ends respectively connected to a bitline and the pull-up transistors, a leakage current compensating part having ends respectively connected to the bitline, a leakage current compensation control part connected to the leakage current compensating part and a first power source, for controlling power supply to the leakage current compensating part, and a leakage current storing part connected to a control terminal of the leakage current compensating part and a second power source for storing a leakage current from the bitline, and controlling the leakage current compensating part according to an amount of a stored leakage current.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4661927 (1987-04-01), Graebel
patent: 5163428 (1992-11-01), Pless
patent: 5414663 (1995-05-01), Komarek et al.
patent: 5650979 (1997-07-01), Komarek et al.
patent: 5748530 (1998-05-01), Gotou et al.
patent: 5835414 (1998-11-01), Hung et al.
patent: 5999451 (1999-12-01), Lin et al.
patent: 6314028 (2001-11-01), Kono
patent: 2001/0034093 (2001-10-01), Matsuzaki et al.

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