Bitline precharge timing scheme to improve signal margin

Details Bitline precharge timing scheme to improve signal margin Bitline precharge timing scheme to improve signal margin

2005-06-14

2005-06-14

Mai, Son (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S203000

Reexamination Certificate

active

06906945

ABSTRACT:
A memory circuit and method to improve signal margin is disclosed. The circuit includes a memory array arranged in rows702, 704, 706and columns750, 752of memory cells. Each row of memory cells is connected to a respective wordline. Each column of memory cells is connected to one of a bitline and a complementary bitline. An active wordline accesses a respective row of memory cells. The memory circuit includes a plurality of precharge circuits724, 726, 728. Each precharge circuit is connected to a respective column of memory cells and coupled to receive a precharge signal PRE. An active precharge signal renders a respective precharge circuit conductive. A control and decode circuit700changes an inactive wordline signal to an active wordline signal while the precharge signal is active.

REFERENCES:
patent: 5467302 (1995-11-01), Hirano et al.
patent: 5675530 (1997-10-01), Hirano et al.
Ali Sheikholeslami et al.,A Survey of Circuit Innovations in Ferroelectric Random-Access Memories,Proc. of the IEEE, vol. 88, No. 5, 667 (May 2000).
Ali Sheikholeslami,Ferroelectric Memory Design(FeRAM 101), ISSCC 2002 Tutorial (Feb. 3, 2002).

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