Bitline contact structures and DRAM array structures

Details Bitline contact structures and DRAM array structures Bitline contact structures and DRAM array structures

1998-06-08

2000-01-18

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257309, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

060159839

ABSTRACT:
The invention encompasses DRAM constructions, capacitor constructions, conductive contacts, integrated circuitry, methods of forming DRAM constructions, and methods of forming capacitor constructions. The invention includes a method of forming a contact to a node location comprising: a) forming an electrically insulative layer over a node location; b) patterning a masking layer over a portion of the insulative layer to form an unmasked portion and a masked portion of the insulative layer; c) removing parts of the masked and unmasked portions of the insulative layer to form a first opening over the node location which underlies a portion of the masking layer; d) forming an etch restriction layer within the first opening and over the masking layer; e) forming a sacrificial spacer layer within the first opening and over the etch restriction layer; f) forming a second opening extending from the first opening to the node location; and g) forming an electrically conductive pedestal within the first and second openings and in electrical connection with the node location. The invention also includes a capacitor comprising: a) an electrically conductive pedestal in electrical contact with a node location, the pedestal, viewed laterally in cross-section, comprising a pair of opposing lateral surfaces; b) an inner electrically conductive layer laterally against both lateral surfaces; c) a capacitor dielectric layer laterally against the inner conductive layer; and d) an outer electrically conductive layer laterally against the capacitor dielectric layer.

REFERENCES:
patent: 4845537 (1989-07-01), Nishimura et al.
patent: 4864374 (1989-09-01), Banerjee
patent: 5084416 (1992-01-01), Ozaki et al.
patent: 5170233 (1992-12-01), Liu et al.
patent: 5180689 (1993-01-01), Liu et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5227325 (1993-07-01), Gonzalez
patent: 5229310 (1993-07-01), Sivan
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5244826 (1993-09-01), Gonzalez et al.
patent: 5270968 (1993-12-01), Kim et al.
patent: 5283455 (1994-02-01), Inoue et al.
patent: 5294296 (1994-03-01), Yoon et al.
patent: 5323038 (1994-06-01), Gonzalez et al.
patent: 5334862 (1994-08-01), Manning et al.
patent: 5338700 (1994-08-01), Dennison et al.
patent: 5385855 (1995-01-01), Manabe
patent: 5401681 (1995-03-01), Dennison
patent: 5444013 (1995-08-01), Akram et al.
patent: 5482886 (1996-01-01), Park et al.
patent: 5516710 (1996-05-01), Boyd et al.
patent: 5527738 (1996-06-01), Kohet et al.
patent: 5545584 (1996-08-01), Wuu et al.
patent: 5622883 (1997-04-01), Kim
patent: 5623243 (1997-04-01), Watanabe et al.
patent: 5629539 (1997-05-01), Aoki et al.
patent: 5700731 (1997-12-01), Lin et al.
patent: 5712202 (1998-01-01), Liaw et al.
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5796573 (1998-08-01), Kotecki et al.
patent: 5874756 (1999-02-01), Ema et al.
Sakao, M., "A Capacitor-Over-Bit-Line (COB) Cell With a Hemispherical-Grain Storage Node for 64Mb DRAMs", 1990 IEEE, pp. 27.3.1--27.3.4.
Aoki, M., et al., "Fully Self-Aligned 6F.sup.2 Cell Technology for Low Cost 1Gb DRAM", 1996 IEEE, pp. 22-23.
IBM Technical Disclosure Bulletin, "Methods of Forming Small Contact Holes", vol. 30, No. 8 (Jan. 1988), pp. 252-253.
U.S. application No. 08/163,439, Dennison, filed Dec. 7, 1993.
U.S. application No. 08/662,591, Dennison, filed Mar. 20, 1994.
U.S. application No. 08/394,545, Jost et al., filed Feb. 22, 1995.
U.S. application No. 08/394,546, Jost et al., filed Feb. 22, 1995.
U.S. application No. 08/558,643, Figura et al., filed Nov. 13, 1995.
U.S. application No. 08/582,385, Sandhu et al., filed Jan. 3, 1996.
U.S. application No. 08/612,164, Dennison, filed Mar. 7, 1996.
Hayden, J.D., et al., "A New Toroidal TFT Structure for Future Generation SRAMs", IEEE 1993, pp. 825-828, IEDM.
U.S. application No. 08/277,916 Dennison, filed Jul. 20, 1994.
U.S. application No. 08/397,885, Blalock et al., filed Mar. 3, 1995.
U.S. application No. 08/078,616, Lee et al., filed Jun. 17, 1993.
U.S. application No. 08/440,212, Fischer et al., filed May 12, 1995.
U.S. application No. 07/869,615, Doan et al., filed Apr. 16, 1992.
U.S. application No. 08/000,891, Doan et al., filed Jan. 5, 1993.
U.S. application No. 08/047,668, Dennison et al., filed Apr. 14, 1993.
U.S. application No. 08/044,824, Dennison et al., filed Apr. 7, 1993.
U.S. application No. 08/055,085, Sandhu et al., filed Apr. 29, 1993.

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