Bitline booster circuit and method

Details Bitline booster circuit and method Bitline booster circuit and method

2006-09-12

2006-09-12

Tran, Michael T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S203000

Reexamination Certificate

active

07106635

ABSTRACT:
A circuit and method for boosting bitline performance uses a bitline booster circuit to allow long bitlines, with large numbers of memory cells attached, to discharge to a digital zero in a faster time. One bitline booster circuit requires only two additional NOR gates, two additional transistors, and one additional control signal. Consequently, the bitline booster circuit does not require a significant number of added components, does not require multiple control signals and takes up minimal additional silicon area.

REFERENCES:
patent: 4982367 (1991-01-01), Miyatake
patent: 5115412 (1992-05-01), Tobita
patent: 5173877 (1992-12-01), Flannagan et al.
patent: 5255235 (1993-10-01), Miyatake

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