Bitline bias circuit for non-volatile memory devices

Details Bitline bias circuit for non-volatile memory devices Bitline bias circuit for non-volatile memory devices

1999-02-23

2000-04-11

Phan, Trong

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518518, G11C 1604

Patent

active

060494913

ABSTRACT:
A bitline bias circuit, particularly for non-volatile memories, is disclosed. The bitline bias circuit includes an inverting stage which drives a first cascode transistor for biasing a selected bitline. A terminal of the first cascode transistor is fed back as an input to the inverting stage so as to form a first feedback loop. The bitline bias circuit further includes a second cascode transistor having a control terminal driven by the output of the inverting stage and a terminal which is fed back as an input to the inverting stage, thereby forming a second feedback loop. The feedback loops eliminate oscillations appearing on internal signals so as to reduce memory cell read cycle times.

REFERENCES:
patent: 5226013 (1993-07-01), Secol et al.
patent: 5706240 (1998-01-01), Fiocchi et al.
patent: 5768206 (1998-06-01), McClure
patent: 5805509 (1998-09-01), Leung et al.
patent: 5886931 (1999-03-01), Hashiguchi
patent: 5907510 (1999-05-01), Sheffield et al.

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