Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
1999-10-25
2001-04-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S207000, C327S051000, C327S052000
Reexamination Certificate
active
06215713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of this invention relates to circuits, systems and methods dealing with sense amplifiers and more particularly to circuits, systems and methods relating to static, low-power differential sense amplifiers.
2. Description of Related Art
Conventional semiconductor memories include memory cells arranged in one or more memory cell arrays. The memory cells are accessed by the user specifying particular row and column addresses. The row and column addresses cause selection of particular cells in the memory cell array subject to specified row and column addresses. The row and column addresses thus permit access to selected individual cells or groups of cells. The information stored in the selected cells may be output by a read operation or input by a write operation. A sense amplifier is activated in a read operation to sense information stored in particular memory cells and to provide an output signal indicative of that particular information content. This output signal may be provided to other circuitry within the memory device and ultimately to an external device which has requested the read information. Such an external device may for example be a data processing or computer system. Memory devices of the related art have in some cases required enable signals to control the timing of sensing operation performed by the sense amplifiers in a read operation. Such timing control requirements increase memory circuit complexity and consume increased amounts of silicon area required for layout and placement of memory device circuitry on a selected integrated circuit during fabrication. This increased silicon size creates technical difficulties and makes manufacturing more expensive, because the cost of memory devices is at least in part a function of silicon size.
Conventional static differential sense amplifiers moreover often consume excessive power and draw electric current beyond the power levels which optimize battery lifetime. This creates technical problems for mobile computer systems which need extended battery lifetimes. Excessive power consumption unfortunately decreases battery lifetime. The technical problems of excessive currents and high power consumption unfortunately diminish the commercial demand and the functionality of the associated static random access memories (RAMs) whether used in mobile computer systems or otherwise.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, an amplifier is connected to first and second complementary bitlines of semiconductor memory which carries selected information in particular memory cells. The amplifier according to this embodiment of the present invention comprises first and second control circuits which are connected to the first and second complementary bitlines to control the application of a first voltage according to the logical states of the bitlines. The amplifier further comprises first and second nodes which are connected to corresponding control circuits. Further, the amplifier comprises cross-coupled circuits connected to the control circuits, to produce output signals representative of information in particular cells of the semiconductor memory.
According to the present invention, a differential sense amplifier (DSA) includes first and second crosslinked sense amplifier channels having pull-up transistors and complementary differential nodes (CDNs) which are separated from ground by respective sense amplifier (SA) parallel transistor (PT) pairs. Prior to undertaking read operation, each of the complimentary differential nodes are set to a low logical state. Each channel of the DSA according to one embodiment of the present invention includes a pair of series connected transistors, one of the series connected transistors being controlled by an input bitline or its complement, and the other of the series connected transistors according to one embodiment of the present invention being controlled by a read enable signal provided over a read line. The differential nodes are linked to one of the transistors of the PT pair of the opposite channel (i.e., the linking transistor), so that when a particular differential node goes high, its complementary differential node is ground connected through the particular linking transistor to produce a complementary low at the complementary differential node. Further according to the present invention, the DSA includes first and second output channels having complementary output nodes (CONs) which are separated from ground by respective parallel transistor (PT) groups, each PT group being controlled at one of its transistors by a corresponding one of the complementary differential nodes of the first and second crosslinked channels. The DSA according to one embodiment of the present invention further includes first and second logic gates (LGs) to produce a differential sense amplifier output. Each of the respective LGs according to this embodiment is driven by a corresponding one of the CDNs and an opposite one of the CONs. According to another embodiment of the present invention, the DSA includes first and second control transistors connected to a done line and respectively activated by corresponding ones of said CDNs. The done line indicates completed performance of sensing operation by the DSA. In accordance with the present invention, a self-timed sense amplifier for a memory device generates a completion signal to indicate when a read or write operation has been completed and does not require an enable signal to time its sense operation. In addition, a memory device according to one embodiment of the present invention includes control circuitry connected to the self-timed sense amplifier. In a further embodiment, the memory device may include latch circuitry connected to the self-timed sense amplifier such that the memory device draws little static current and provides reduced power consumption during operation. The present invention further includes a corresponding method for accessing memory cells within an array of memory cells.
REFERENCES:
patent: 5650971 (1997-07-01), Longway et al.
patent: 5668765 (1997-09-01), Ang
patent: 5696726 (1997-12-01), Tsukikawa
Cirrus Logic Inc.
Ho Hoai V.
Nelms David
Rutkowski Peter T.
Stewart David L.
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