Bit synchronizing circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

375355, 375354, 370503, H03D 324

Patent

active

059094737

ABSTRACT:
In a bit synchronizing circuit, the oscillating operation is prevented in the phase synchronizing stage such that even the reception data including a phase variation such as a jitter component can be appropriately reproduced. A phase comparator compares the phase of reception data with that of each of the n-phase clock signals to produce clock phase information. An averaging circuit obtains mean value data of the clock phase information. D-type flip flop circuits achieve sampling operations of the reception data and latch therein n sampling data items to be thereafter outputted. A data selector selects one of the n sampling data items according to the mean value data of clock phase information and delivers therefrom the selected item as selection data. A clock selector selects one of the n-phase clock signals in association with the average data of clock phase information and then outputs the selected item as an extraction clock signal.

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patent: 5638411 (1997-06-01), Oikawa
patent: 5642387 (1997-06-01), Fukasawa
patent: 5657318 (1997-08-01), Ohmori et al.

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