Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1996-02-02
1997-06-24
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
36518904, H04L 700, H04L 2536, H04L 2540
Patent
active
056423870
ABSTRACT:
A bit synchronization circuit receives a first clock signal, a higher-frequency second clock signal, and digital data synchronized with the first clock signal. From the first clock signal, the circuit generates a write control signal that cyclically selects memory elements from a group of memory elements, and stores the digital data in the selected memory elements. From the second clock signal, the circuit generates a read control signal that cyclically selects memory elements from the same group, and outputs the digital data from the selected memory elements. The circuit also compares the phase of the read and write control signals, and adjusts the phase of the read control signal in response to the phase relation between the write control signal and read control signal.
REFERENCES:
patent: 5119406 (1992-06-01), Kramer
patent: 5247485 (1993-09-01), Ide
patent: 5283787 (1994-02-01), Fletcher et al.
patent: 5353313 (1994-10-01), Honea
patent: 5502750 (1996-03-01), Co et al.
patent: 5563891 (1996-10-01), Wang
"A study of bit synchronization circuit for high-speed switching systems" Technical Paper of the IEICE of Japan, SSE89-114, NTT Communication Switching Labs, Otsuka et al., pp. 37-42.
"Bit Synchronization Circuit for High-Speed Switching Systems," Transactions of the IEICE of Japan B-I, vol. J74-B-1, No. 4, pp. 304-312, 1991 Otsuka et al.
Chin Stephen
Lee Betsy P.
OKI Electric Industry Co., Ltd.
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