Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-01-27
2002-04-16
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C327S152000, C359S199200
Reexamination Certificate
active
06373911
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a bit synchronization circuit. More specifically, the invention relates to a bit synchronization circuit for a optical receiver in a large scale optical interconnection network in a passive double star (PDS) system, a large scale computer, a large capacity Asynchronous Transfer Mode (ATM) switch.
2. Description of the Related Art
In a large capacity optical interconnection network employing an optical switch, signals from respective nodes are switched by the optical switch. Since distances between respective nodes are not equal to each other, bit synchronization has to be re-established in a receiver upon switching of the optical switch. A synchronization period is desired to be less than or equal to 10 bits so as not to lower throughput.
On the other hand, in order to enlarge the scale of network, high sensitivity of an optical receiver in each node is desired. Therefore, similarly to the conventional transmission system, assuming a transmission speed is A bit/s, a band of the optical receiver is set about 0.8×A Hz to eliminate unnecessary high-frequency noise to improve receiver sensitivity. On the other hand, a semiconductor optical amplifier gate is employed in the switching element, for influence of amplified spontaneous emission noise of the element, the optical receiver in each node is required a phase precision of an decision clock at about ±10% of one time slot.
Conventionally, as the bit synchronization method, there have been known a method using a Phase Locked Loop (PLL), a method using a timing tank, a method using a gated voltage controlled oscillator (gated VCO) and a method using a multi-phase clocks.
PLL is a method to control voltage of a voltage controlled oscillator (VCO) so as to eliminate a phase difference by phase comparison of a received signal and an output clock of VCO. The synchronization period depends on a response period of a loop and generally becomes micro-second order, about 10,000 bits at 10 Gb/s.
The timing tank is a method to establish bit synchronization by differentiating a received signal, rectify the differentiated output into all positive pulse (or negative pulse), and pass the output through a band pass filter (BPF). It has been known that assuming a Q factor of BPF is Q
0
, the synchronization period becomes substantially Q
0
bits. In general, a Q factor is typically set to be greater than or equal to 100 in order to obtain clock with small jitter, the synchronization period becomes greater than or equal to 100 bits.
The method with gated VCO is an open loop method using rising and falling signal of the received data, which permits synchronization at 1 bit but has no jitter rejection effect.
On the other hand, in the bit synchronization circuit employing the multi-phase clocks, establishment of synchronization at several bits and rejection of jitter become possible. For example, in Japanese Unexamined Patent Publication No. Heisei 7-193562, the bit synchronization circuit includes a clock multi-phase clock generator outputting a plurality of N phase clock signals from a reference clock, a clock selection circuit inputting a received data and multi-phase clock output from the multi-phase clock generator to select the clock for decision, and an elastic storage reading out the received data with taking the clock output from the clock selection circuit as writing reference clock. By deciding received data using the selected clock by the clock selection circuit, bit synchronization is established.
In the conventional bit synchronization circuit selected an optimal phase from the multi-phase clocks, the clock of the optimal phase is selected in a logic circuit which takes the received data and a plurality of phases of clocks to decide the received data using the selected clock. At least several tens ps of delay is present per one gate of the circuit, a difference of hundred ps or more should be present in a phase relationship of data input to the clock selection circuit and the clock and in phase relationship of data input to an identifier and the clock.
However, since in a high speed range where a transmission speed of data is higher than or equal to several Gb/s, a period per one time slot becomes several hundreds ps, if difference in the phase relationship between the data input to the clock selection circuit and the clock and the phase relationship between the data input to the identifier and the clock become greater than or equal to 100 ps, decision phase of the identifier cannot be correct.
In case of a construction to compensate the phase difference by a gate delay, since fluctuation of the gate delay is at least ±20%, ±20 ps or more fluctuation is inherently caused. In case of 10 Gb/s, fluctuation of phase in the extent of ±20 ps results in degradation of receiver sensitivity more than or equal to 4 dB to make it difficult to put into practical use. On the other hand, in order to realize high speed operation higher than or equal to several Gb/s, operation speed of the circuit is close to extreme to be inoperative for too small amplitude unless a load capacity is made as small as possible. For this reason, a complicate logic circuit cannot be constructed because fan out number of the gate cannot be set large, wiring line of the signal line cannot be set long, the gate delay becomes about one half of one time slot and so forth.
Furthermore, unless the elastic storage is present, the phase of the data to be output can be differentiated depending upon the clock phase to cause dropout in the later stage to possibly cause malfunction. However, elastic storage operated at high speed as high as several Gb/s or higher is difficult to realize.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a bit synchronization circuit which can operate within a high speed region as high as one Gb/s or higher without causing degradation of sensitivity due to phase deviation, with constant in phase of data to be output and can establish synchronization within 10 bit and has jitter rejection effect.
According to one aspect of the present invention, a bit synchronization circuit comprises:
multi-phase clock generating means for generating mutually different phases of plurality of clocks in synchronism with input reference clock;
a plurality of decision means for respectively deciding input data using different phases output from the multi-phase clock generating means as data decision clock;
phase comparator means for performing phase comparison between the input data and respective clocks of different phases output from the multi-phase clock generating means;
phase determining means for determining the clock occurring level transition timing at substantially center portion of mutually adjacent level transition timings of the input data depending upon a plurality of phase comparison outputs of the phase comparator means; and
selection means for selecting and outputting an output of the decision means taking the clock determined by the phase determining means as the data decision clock,
phase of the input data to the phase comparator means and the decision means being the same and phases of the clocks to the phase comparator means and the decision means being the same.
The bit synchronization circuit may further comprise holding means responsive to an external command signal for holding a result of determination of the phase determining means, and the selection means is controlled according to a holding output of the holding means.
Also, the bit synchronization circuit may further comprises delay means for making respective output timings from the decision means equal to each other.
In the preferred construction, each of the decision means may be a D-type flip-flop taking the input data as data input and the clock as clock input. Also, the phase comparator means may be a plurality of D-type flip-flops taking the clocks as respective data inputs and the input data as clock inputs.
The phase determining mean
Araki Soichiro
Henmi Naoya
Maeno Yoshiharu
Suemura Yoshihiko
Tajima Akio
Ostrolenk Faber Gerb & Soffen, LLP
Pham Chi
Phu Phuong
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