Bit switch circuit and bit line selection method

Details Bit switch circuit and bit line selection method Bit switch circuit and bit line selection method

1998-06-19

1999-10-05

Mai, Son

Static information storage and retrieval

Read/write circuit

For complementary information

365205, G11C 700

Patent

active

059634863

ABSTRACT:
A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).

REFERENCES:
patent: 4888732 (1989-12-01), Inoue et al.
patent: 4922460 (1990-05-01), Furutani et al.
patent: 5570319 (1996-10-01), Santoro et al.
patent: 5748547 (1998-05-01), Shau
Richard Guo, Terry Y. Su and Chia Chi Chao, "A 500 Mhz 1Mb On-Chip Cache Design Using Multi-Level Bit Line Sensing Scheme", 1996 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 130-131.

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