Bit set modes for a resistive sense memory cell array

Details Bit set modes for a resistive sense memory cell array Bit set modes for a resistive sense memory cell array

2009-01-13

2011-10-18

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Systems using particular element

Resistive

C365S100000, C365S145000, C365S158000, C365S171000

Reexamination Certificate

active

08040713

ABSTRACT:
Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

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