Optical communications – Receiver
Reexamination Certificate
2000-10-30
2004-01-27
Negash, Kinfe-Michael (Department: 2633)
Optical communications
Receiver
C398S214000, C398S027000, C375S225000, C375S327000
Reexamination Certificate
active
06684033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to bit rate detection circuits for optical networks, and in particular, to methods and bit rate detection circuits for automatically detecting data bit rates to enhance end-to-end transparency and suppress jitters in optical networks.
2. Description of the Related Art
In a wavelength-division multiplexing (WDM) and erbium-doped fiber amplifier (EDFA) optical network system, jitters accumulate in the system as transmitted data pass through different modules in the system, and such accumulation of jitters affects the end-to-end transparency of the WDM system. As jitters accumulate in a system, the error rate in the system also increases, and a typical digital system may tolerate only 10
−12
error rate. To suppress the jitters that occur in optical networks, optical networks typically employ clock and data recovery (CDR) circuits to extract and regenerate clock signals and retime the data by using the extracted clock signal.
FIG. 1
illustrates a prior art receiver
10
in an optical network for receiving transmitted data signals. The receiver
10
includes a photo diode
11
, a low-noise amplifier
12
, a limiting amplifier
13
and a CDR circuit
15
. The photo diode
11
receives optical input data signals emanating from an optical fiber and converts the optical light energy in the input data signals into a low-level electrical current which can be used to produce electrical signals. The low-noise amplifier
12
receives the low-level signal current from the photo diode
11
and amplifies the signal so that additional processing will not add significantly to the noise in the signal. The low-noise amplifier
12
converts the low-level signal current into a voltage signal for subsequent processing. A transimpedance amplifier
20
shown in
FIG. 2
a
may be used as the low-noise amplifier
12
. In addition, the low-noise amplifier
12
reduces the bandwidth of the signal outputted by the photo diode
11
. Basically, the low-noise amplifier
12
functions similar to a low pass filter except that the low-noise amplifier
12
has a much higher cutoff frequency than a typical low pass filter, e.g., 2.8 GHz.
The limiting amplifier
13
receives the output of the low-noise amplifier
12
and serves to buffer the receiver
10
from process variations and changes in signal strength. The limiting amplifier
13
also performs noise shaping. The limiting amplifier
13
contains either a limiter or an automatic-gain-control circuit to provide a proper signal level to the CDR
15
, regardless of the output power of the low-noise amplifier
12
. The limiting amplifier
13
outputs a constant-level output voltage, Vconst if the input voltage level is above a certain threshold value, Vth, as shown in
FIG. 2
b
. Thus, even if the input signal has low amplitude and power, the limiting amplifier
13
will bring the input signal up to a proper amplitude and power level.
The CDR
15
recovers the timing information from the input data signal and samples the input data stream from the limiting amplifier
13
at an appropriate timing or instant.
FIG. 2
c
illustrates a block diagram of a typical CDR
30
which may be used for the CDR
15
. The CDR
30
uses a phase-lock loop (PLL)
31
to recover the clock from the input data signal. The CDR
30
includes an edge detector
35
, a phase-lock loop (PLL)
31
and a decision circuit
36
which may be a D flip-flop. The PLL
31
includes a phase detector
32
, a loop filter
33
and a voltage controlled oscillator (VCO)
34
. The output of the PLL
31
is inputted into the decision circuit
36
. In the CDR
30
, the edge detector
35
first receives the input data signal, and then the input-data derived signal from the edge detector
35
is inputted into the phase detector
32
which functions as a mixer to heterodyne the edge-detected input signal down to the baseband. The phase detector
32
receives the input-data derived signal from the edge detector
35
and a clock signal outputted by the VCO
34
and produces a voltage proportional to the phase difference between the input-data derived signal from the edge detector
35
and the clock signal from the VCO
34
. The output of the phase detector
32
is inputted into the loop filter
33
, and the loop filter
33
outputs a control signal which controls the clock of the VCO
34
. The above process is repeated until the phase difference is driven to zero (i.e., until the frequency or phase difference between the input data signal and the clock signal of the VCO
34
is near or at zero).
In other words, the PLL
31
basically tracks the phase of the edge detected signal by using the phase detector
32
to produce a phase-error signal, filters the phase-error signal with the loop filter
33
and adjusts the frequency of the VCO
34
by using the filtered signal so that the frequency of the VCO
34
is synchronized to the input data rate (i.e., the data rate or frequency of the input signal). The output of the VCO
34
, which is the regenerated clock signal of the input data signal, is inputted into the decision circuit
36
which may be a D flip-flop so that the input data is sampled at a correct rate. In other words, assuming the decision circuit
36
is a D flip-flop, the output of the VCO
34
is inputted into the CK (clock) input of the D flip-flop so that the input data signal received by the D flip-flop is retimed or sampled at a correct frequency.
Although the prior art receiver
10
functions properly if the input data rate is fixed at a certain frequency such as 155 Mbps or 1.25 Gbps, the prior art receiver
10
will have problems processing the input data signal if the frequency of the input data signal (i.e., input data rate) varies over a wide range because the frequency of the VCO
34
needs to be set at a rate that approximately matches the frequency of the input data signal. For example, if the input data rate is 2.5 Gbps and the frequency of the VCO is set at 155 MHz, the receiver
10
will not be able to process the input data signal because the PLL
31
will not lock with the input signal since the frequency of the VCO is totally mismatched with the input signal data rate. A VCO having a clock frequency of 155 MHz will not be able to produce a clock signal having a frequency of 2.5 GHz. However, in today's communication systems, signal data rates vary over a wide range from 125 Mbps to 10 Gbps. Thus, if the prior art receiver
10
is used to receive input data signals that have widely varying frequency rates, the frequency of the VCO
34
needs to be manually changed every time to approximately match the input signal data rate if the frequency of the input signal changes dramatically, and such resetting of the VCO frequency can be a cumbersome process which may hinder the smooth operation of the receiver
10
.
Therefore, there is a need for a receiver that automatically detects the frequency of the input data signal, adjusts the frequency of the VCO automatically with respect to the changes in the frequency of the input data signal, and retains the transparency of the input data while suppressing jitters.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a receiver in an optical network with a bit rate detection circuit for automatically detecting input signal data bit rates to automatically adjust the frequency of a voltage controlled oscillator in the receiver, which obviate for practical purposes the above mentioned limitations.
A receiver in accordance with an embodiment of the present invention has a data rate detection and frequency adjustment circuit which automatically detects the data rate of an input signal and automatically adjusts the frequency of a VCO in the receiver in accordance with the data rate of the input signal.
The receiver first receives an input signal through a photo diode. The photo diode outputs a low level current corresponding to the input signal, and a low noise amplifier converts the low level current into a voltage signal for subse
Doh Hee-Chan
Kim Chan-Youl
Oh Yun-Je
Park Gil-Young
Park Tae-Sung
Cha & Reiter
Negash Kinfe-Michael
Samsung Electronics Co,. Ltd.
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