Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1998-03-19
2002-03-12
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C370S505000
Reexamination Certificate
active
06356611
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the recording and/or reading of a digital data stream.
The invention applies more particularly to the case where the data stream is a high bit rate uninterrupted stream such as, for example, a data stream in the MPEG II format.
The recording and reading of digital data can be performed either with the aid of digital recorders, or with the aid of digital video recorders.
As will become apparent in the remainder of the description, the invention finds a particularly advantageous application with regard to the recording and reading of digital data with the aid of digital video recorders. However, the invention applies equally to the recording and reading of digital data with the aid of digital recorders.
SUMMARY OF THE INVENTION
Thus, the invention relates to an interface for controlling the bit rate of digital data to be recorded. The control interface comprises at least one memory circuit for storing the data to be recorded and means whereby the data to be recorded can be stored in the memory circuit in such a way as to fill the memory circuit to a predetermined level under the action of a write command, of a read command and of a reset to zero command for a level indicator of the memory circuit, these commands being applied to the memory circuit.
Similarly, the invention relates to an interface for controlling the bit rate of digital data emanating from a reading device. The control interface comprises at least one memory circuit for storing the data to be read and means whereby the data to be read can be stored in the memory circuit in such a way as to fill the memory circuit to a predetermined level under the action of a write command, of a read command and of a reset to zero command for a fill level indicator for the memory circuit, these commands being applied to the memory circuit.
The invention also relates to a digital data recording system consisting of a control interface for the bit rate of data to be recorded and of a device for recording the digital data emanating from the control interface. The interface for controlling the bit rate of the data to be recorded is an interface such as that according to the invention mentioned above.
The invention also relates to a digital data reading system consisting of a device for reading digital data and a control interface for the bit rate of the digital data emanating from the reading device. The control interface for the bit rate of the digital data emanating from the reading device is a control interface such as that according to the invention mentioned above.
The invention also relates to a digital data recording/reading system comprising a control interface for the bit rate of digital data to be recorded, a recording/reading device and a control interface for the bit rate of digital data emanating from the recording/reading device. The control interface for the bit rate of digital data to be recorded is a control interface such as that according to the invention mentioned above and the control interface for the bit rate of the digital data emanating from the recording/reading device is an interface such as that according to the invention mentioned above.
REFERENCES:
patent: 4718074 (1988-01-01), Mannas et al.
patent: 4759041 (1988-07-01), Anderson et al.
patent: 5007070 (1991-04-01), Chao et al.
patent: 5027351 (1991-06-01), De Prycker et al.
patent: 5486784 (1996-01-01), Eriksson
patent: 5534929 (1996-07-01), Tanaka
patent: 5566208 (1996-10-01), Balakrishnan
patent: 5708686 (1998-01-01), Assus et al.
patent: 5742400 (1998-04-01), Satoh
patent: 5754241 (1998-05-01), Okaka et al.
patent: 6097876 (2000-09-01), Ohishi et al.
patent: 6115537 (2000-09-01), Yamada et al.
patent: 6124999 (2000-09-01), Yamamoto
patent: 0560020 (1993-09-01), None
patent: 98400677 (1998-07-01), None
patent: 2304501 (1997-03-01), None
IBM Technical Disclosure Bulletin, vol. 36, No. 10 Oct. 1, 1993 pp. 569-570 Programmable High Performance Memory Buffer.
Civanlar M R Et Al. “A Practical system for MPEG-2-based video-on-demand over ATM packet networks and the WWW” Signal Processing Image Communication, vol. 8, No. 3 Apr. 1996, pp. 221-227.
Bourdon François
Chapel Claude
Quintard Jean-Yves
Chin Stephen
Ha Dac V.
Kurdyla Ronald H.
Thomson Licensing S.A.
Tripoli Joseph S.
LandOfFree
Bit rate control interface for the recording and/or reading... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bit rate control interface for the recording and/or reading..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit rate control interface for the recording and/or reading... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2867562