Bit phase synchronizing circuitry for controlling phase and freq

Details Bit phase synchronizing circuitry for controlling phase and freq Bit phase synchronizing circuitry for controlling phase and freq

1996-09-17

1999-07-06

Le, Amanda

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

327149, 327158, H03D 324

Patent

active

059206004

ABSTRACT:
In bit phase synchronizing circuitry, received data with an unknown phase and triphase clocks output from a reset VCO (Voltage Controlled Oscillator) are input to a timing decision circuit. If preselected one of the triphase clocks and the received data have an adequate relation, the decision circuit causes the current clock phase to be maintained. If otherwise, the decision circuit determines whether the current clock phase should be advanced or retarded. The resulting decision signal output from the decision circuit is fed to a selector controller. The decision circuit latches the received data with the preselected one of the triphase clocks and outputs them together with the clock used for latching. A phase controller causes the reset VCO to selectively operate in a phase shift mode or in a multiplication PLL (Phase Locked Loop) mode. The circuitry is capable of setting up bit phase synchronization stably and rapidly with a simple configuration without regard to the phase of the received data. In addition, the circuitry is little susceptible to noise.

REFERENCES:
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5446766 (1995-08-01), Wray
patent: 5687203 (1997-11-01), Baba
"A 150/30 Mb/s CMOS Non-Oversampled Clock and Data Recovery Circuits with Instantaneous Locking and JItter Rejection", 1995 IEEE International Solid-State Circuits Conference, Feb. 1995.
"A 660Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission", 1993 IEEE International Solid-State Circuits Conference, Feb. 1993.
"A Bit Synchronization Circuit for Burst Signals for High Speed PDS Systems", Technical Report, The Institute of Electronics, Information and Communication Engineers, Sep. 1995.
"A 45-Mbit/s CMOS VLSI Digital Phase Aligner", IEEE Journal of Solid-State Circuits, Apr. 1988.

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