Bit map addressing schemes for flash/memory

Details Bit map addressing schemes for flash/memory Bit map addressing schemes for flash/memory

1997-05-02

1998-07-14

Dinh, Son T.

Static information storage and retrieval

Floating gate

Particular connection

36523003, G11C 800

Patent

active

057814724

ABSTRACT:
Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected memory cell are read in parallel. "By-address" architectures provide one address per bit such that each selected memory cell is mapped to one output, and the n bits stored in the selected memory cell are read sequentially.

REFERENCES:
patent: 4202044 (1980-05-01), Beilstein, Jr. et al.
patent: 4287570 (1981-09-01), Stark
patent: 4388702 (1983-06-01), Sheppard
patent: 4415992 (1983-11-01), Adlhoch
patent: 4460982 (1984-07-01), Gee et al.
patent: 4586163 (1986-04-01), Koike
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4701884 (1987-10-01), Aoki et al.
patent: 4771404 (1988-09-01), Mano et al.
patent: 4875188 (1989-10-01), Jungroth
patent: 4943948 (1990-06-01), Morton et al.
patent: 5012448 (1991-04-01), Matsuoka et al.
patent: 5043940 (1991-08-01), Harari
patent: 5095344 (1992-03-01), Harari
patent: 5163021 (1992-11-01), Mehrotra
patent: 5172338 (1992-12-01), Mehrotra
patent: 5218569 (1993-06-01), Banks
patent: 5260901 (1993-11-01), Nagase et al.
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5283761 (1994-02-01), Gillingham
patent: 5287305 (1994-02-01), Yoshida
patent: 5289406 (1994-02-01), Uramoto et al.
patent: 5289412 (1994-02-01), Frary et al.
patent: 5293560 (1994-03-01), Harai
patent: 5297148 (1994-03-01), Harari
patent: 5305273 (1994-04-01), Jinbo
patent: 5351210 (1994-09-01), Saito
patent: 5361343 (1994-11-01), Kosonocky et al.
patent: 5375097 (1994-12-01), Reddy et al.
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5430676 (1995-07-01), Ware et al.
patent: 5434817 (1995-07-01), Ware et al.
patent: 5438546 (1995-08-01), Ishac et al.
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5463582 (1995-10-01), Kobayashi et al.

Affiliated with

Also associated with

Rating

Bit map addressing schemes for flash/memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit map addressing schemes for flash/memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit map addressing schemes for flash/memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1889601