Bit lines write circuit for SRAM memories

Details Bit lines write circuit for SRAM memories Bit lines write circuit for SRAM memories

1994-09-30

1996-04-02

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365190, 365156, G11C 700

Patent

active

055047114

ABSTRACT:
The write circuit for SRAM memories of this invention includes on each column select line B1,B1' a N-type transistor (N1, N2) which is utilized to drive the voltage on one of the column select lines to V.sub.cc -V.sub.t. A pull-up circuit circuit is also provided with each column select line B1, B1'which includes a P-type transistor (P1,P2) which is coupled to the supply V.sub.cc. This circuit raises the voltage which appears between the two column select lines B1, B1' to V.sub.cc which is used to write data to a SRAM cell 10, 12 disposed therebetween.

REFERENCES:
patent: 5121356 (1992-06-01), Park
patent: 5245579 (1993-09-01), Ohta
patent: 5291447 (1994-03-01), Kodama

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