Bit line voltage regulation circuit

Details Bit line voltage regulation circuit Bit line voltage regulation circuit

2001-12-28

2004-02-24

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185180, C365S185230, C365S189060

Reexamination Certificate

active

06697288

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device; and, more particularly, to a bit line voltage regulation circuit capable of achieving uniform program features and precise cell distribution by providing a high voltage to a bit line regardless of a cell state by detecting a current variation on the bit line depending on the cell state, and a voltage drop caused by resistance on the bit line and feeding back the detected values to a boosting unit having a self-compensating ability.
2. Description of the Related Art
Referring to
FIGS. 1 and 2
, there are shown program features and drain junction features of a flash EEPROM using a hot carrier injection method to store information.
In
FIG. 1
, there is shown a graph representing cell threshold voltages varying according to a program time in case of supplying drain voltages Vd of 4.0 V, 3.5 V, 3.0 V and 2.5 V as changing a temperature condition.
FIG. 2
illustrates a graph depicting a drain current varying as increasing a drain voltage Vd in a condition of determining a gate voltage Vg, a source voltage Vs and a substrate voltage Vb as 0 V.
As shown in
FIG. 1
, when a too low drain voltage is provided to a drain, a cell cannot be programmed. On the other hand, if a too high drain voltage is supplied to the drain, a junction breakdown phenomenon may occur due to a serious drain breakdown as shown in FIG.
2
. Therefore, a cell should be programmed by providing a drain voltage capable of avoiding the above two conditions, and at this time, there should be considered a voltage drop, due to resistance from a boosting unit to a junction unit. When programming the cell, a current flowing from a plurality of cells, e.g., 500 to 1000 cells, sharing a bit line is the sum of the current flowing in a selected cell for the cell program and a leakage current flowing in unselected cells, and the current flowing in the boosting unit is the sum of currents flowing through selected bit lines. Herein, if cells connected to the selected bit line are in a programmed state, there is almost no voltage drop since little current flows through the programmed cells. Specifically, as memory devices are miniaturized and integrated, resistance on a path from the boosting unit to the drain of the flash cell increases.
However, as shown in
FIG. 3
, in case I all of the cells sharing the selected bit line are in a erased state, a serious voltage drop occurs since the current flowing through the selected bit line increases and it is impossible to write information into the cells. On the other hand, in case III all of the cells are programmed, a voltage provided from the boosting unit cannot be properly controlled since no current flows through the bit lines, so that the voltage outputted from the boosting unit shocks on drains of the cells without a voltage drop. Meanwhile, the case II shown in
FIG. 3
represents half of the cells sharing the selected bit line programmed.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a bit line voltage regulation circuit capable of solving problems due to a voltage drop caused by a current difference according to a state of a cell.
In order to achieve the above object, the present invention employs a method for dynamically rectifying an output voltage of a boosting unit by feeding back a voltage drop caused according to a state of a cell to a rectifying block of the boosting unit, thereby minimizing a voltage swing at a drain of the cell.
In accordance with the present invention, there is provided a bit line voltage regulation circuit comprising: a boosting unit for generating a high voltage; a switching unit, connected between the boosting unit and a bit line of a memory cell array, for transferring the high voltage to the bit line; and an amplifying unit for detecting a voltage drop at a detection node on the bit line caused by resistance on the bit line, amplifying the detected voltage drop to produce an amplified voltage driving the switching unit.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5781474 (1998-07-01), Sali et al.
patent: 6184670 (2001-02-01), Mulatti et al.
patent: 6347058 (2002-02-01), Houghton et al.

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