Bit-line voltage limiting isolation circuit

Details Bit-line voltage limiting isolation circuit Bit-line voltage limiting isolation circuit

1998-04-02

1999-08-10

Le, Vu A.

Static information storage and retrieval

Read/write circuit

For complementary information

365205, 365207, G11C 700

Patent

active

059368985

ABSTRACT:
A voltage limiting isolation circuit for pairs of bit lines within a row of DRAM cells to reduce noise coupling will selectively connect and disconnect the portions of a primary and a complementary bit lines, onto which DRAM cells are attached, from the portions of the primary and the complementary bit lines, onto which latching sense amplifier and pre-charge and equalization circuit are attached. The voltage limiting bit line isolation circuit has two sets of serially connected N-type MOS transistors and first P-type MOS transistors placed on the primary bit line and the complementary bit line. Isolation voltage control circuits will provide voltages to the gates of the N-type MOS transistors and P-type MOS transistors to activate and deactivate the voltage limiting isolation control circuit. During a read cycle the latching sense amplifier will sense and amplify the charge from a selected cell and begin to force the first and second portions of the primary and complementary bit lines to a voltage level that is either that of the power supply voltage source or the ground. As the voltage level of the first and second portions of the primary and complementary bit lines approaches to within one threshold voltage level of the MOS transistors, the voltage limiting bit line isolation circuit will deactivate. The first portions of the primary and complementary bit lines will swing to a lower voltage level thus lowering coupled noise to adjacent bit lines.

REFERENCES:
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patent: 5625585 (1997-04-01), Ahn et al.
patent: 5636170 (1997-06-01), Seyyedy
Bellaovar et al. "Low Power digital VLSI design-circuits and systems", Kiuwer Academic, Chapter 6, sec. 6.2.13.1, p. 381-3, 1995.
Aoki et al. "A 60ns, 16Mb, CMOS DRAM with a transposed data-line structure" IEEE Trans. Solid-State Circuits, SC-23, No. 5, p. 1113, 1988.

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