Bit line setup and discharge circuit for programming...

Details Bit line setup and discharge circuit for programming... Bit line setup and discharge circuit for programming...

2002-09-26

2004-11-02

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S226000, C365S185250, C365S203000, C365S204000

Reexamination Certificate

active

06813187

ABSTRACT:

BACKGROUND
1. Field of the Invention
This invention relates to nonvolatile semiconductor memory devices and write or programming processes for nonvolatile semiconductor memory devices.
2. Description of Related Art
EEPROMs, unlike many other nonvolatile memories, can electrically erase old data and write new data. This flexibility in data management makes EEPROMs the preferred nonvolatile memory in system programming, where data may be refreshed and must be available when a system powers up.
A conventional memory cell in an EEPROM includes an N-channel cell transistor, which has a floating gate over a channel region defined between N+ source and drain in a P-type substrate, and a control gate overlying the floating gate. The floating and control gates are made out of a conductive material such as polysilicon, a silicide, or a metal, and insulation layers are between the control and floating gates, and between the floating gate and the channel region.
In flash EEPROM, a common mechanism for erasing and programming memory cells is Fowler-Nordhiem (F-N) tunneling. F-N tunneling changes the threshold voltage of a cell transistor by changing the amount of charge trapped on the floating gate of the cell transistor. For example, an exemplary erase operation applies a high voltage to a substrate while applying a low or negative voltage to the control gate of an N-channel cell transistor. The floating gate, which is between the control gate and the substrate, has a voltage that depends on the net charge trapped on the floating gate, the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate. If the voltage difference between the floating gate and the substrate is larger than a voltage gap required for the F-N tunneling, electrons held in the floating gate tunnel from the floating gate into the substrate. The tunneling of the electrons from the floating gate to the substrate lowers the threshold voltage Vt of the cell transistor.
When the threshold voltage Vt is sufficiently low, the cell transistor conducts a channel current when 0V is applied to the control gate and source of the cell transistor and a positive voltage is applied to drain of the cell transistor. A cell transistor having this lowered threshold voltage is referred to as an “erased cell” or as being in an “erased state,” which represents data value “1”.
In an exemplary programming operation that writes a data value “0” into a cell transistor, a low voltage (e.g., 0V) is applied to the source and drain of the cell transistor, and a high voltage (often more that 10V) is applied to the control gate of the cell transistor. In response, an inversion layer forms in a channel region under the floating gate. This channel region (i.e., the inversion layer) has the same voltage (0V) as the source and drain. When a voltage difference between the floating gate and the channel voltage becomes high enough to cause the F-N tunneling, electrons tunnel to the floating gate from the channel region, thereby increasing the threshold voltage of the cell transistor. A programming operation raises the threshold voltage of a cell transistor high enough to prevent channel current through the cell transistor when a positive read voltage is applied to the control gate, the source is grounded, and a positive voltage is applied to drain. A cell transistor having the raised threshold voltage is referred to as a “programmed cell” or as being in a “programmed state,” which represents data value “0”.
EEPROMs can also achieve the high integration densities necessary for an inexpensive non-volatile memory. In particular, flash EEPROMs achieve high integration density that is adaptable to large capacity subsidiary storage elements, and more specifically, NAND-type flash EEPROMs provide higher integration densities than do the other well-known types of EEPROM (e.g., NOR or AND type EEPROM).
A convention NAND-type EEPROM includes a cell array containing NAND strings, where each NAND string includes a set of cell transistors connected in series.
FIG. 1
shows a conventional NAND-type flash EEPROM
100
including a cell array
110
containing multiple NAND strings
112
. In cell array
110
, each NAND string
112
includes a first select transistor ST, M+1 (e.g., 16) cell transistors M
0
to MM, and a second select transistor GT connected in series. Each first selection transistor ST has a drain connected to a corresponding bit line. Generally, all NAND strings in a column of cell array
110
share the same bit line. The second selection transistor GT in each NAND has a source connected to a common source line CSL for the sector containing the NAND string. Gates of the first and second selection transistors in a row of NAND strings
112
are respectively coupled to a string selection line SSL and a ground selection line GSL corresponding to the row. Each word line in cell array
110
connects to the control gates of all cell transistors in a corresponding row of cell array
110
.
NAND-type flash memory
100
further includes a page buffer including latch circuits
130
, sense circuits (not shown), and a Y or column decoder (Y pass gates
140
). The sense circuits sense the states of selected bit lines to generate output data during a read operation. Latch circuits
130
control the voltages of selected bit lines for a write operation as described further below. An X or row decoder (not shown) activates a string selection line to select a row of NAND strings
112
and a word line that is coupled to the control gates of the cell transistors to be accessed. For reasons described further below, switching transistors
126
and
122
e
or
122
o
connect either the even numbered bit lines or the odd numbered bit lines to the sense circuits or latch circuits
130
. Y pass gates
140
control and select data input/output of sense and latch circuits.
In array
110
, a page includes a set of the cell transistors coupled to a word line associated with the page, and a block or sector is a group of pages. A block can include one or more NAND strings
112
per bit line. Typically, a read or write operation simultaneously reads or programs and entire page of memory cells, and an erase operation erases an entire block or sector.
To program a selected memory cell M
1
in NAND flash memory
100
, a bit line BL
0
assigned to the memory string
112
including a selected memory cell M
1
is biased to 0V. The string selection line SSL for the NAND string
112
containing the selected memory cell M
1
is biased to the supply voltage Vcc to turn on the first selection transistor ST, and the ground selection line GSL is biased to 0V to turn off the second selection transistor GT. The word line WL
1
connected to the control gate of the selected memory cell M
1
is biased to a high voltage. Capacitive coupling between the control gate and the floating gate raises the floating gate to a voltage near the high voltage. In response to the voltage difference between the channel region and the floating gate in the selected memory cell M
1
, electrons from the channel region tunnel into the floating gate of the selected memory cell, thereby increasing the threshold voltage of the selected memory cell M
1
to a positive level.
All control gates of memory cells included in the selected page are at the high voltage for a write operation. However, the page typically includes memory cells that will be programmed to store bit value “0” and other memory cells to be left in the erased state (i.e., are not programmed) and represent data value “1”. To avoid programming a memory cell in the same page as memory cells being programmed, the channel voltage of the memory cell is boosted to reduce the voltage gap between the floating gate and the channel region. The lower voltage gap prevents significant F-N tunneling and keeps the memory cell in the erased state while other memory cells in the same page are programmed.
One useful technique for selectively increasing a channel voltage of a memory cell is often called “self-boost

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