Bit line sensing control circuit for a semiconductor memory devi

Details Bit line sensing control circuit for a semiconductor memory devi Bit line sensing control circuit for a semiconductor memory devi

1993-05-20

1994-12-06

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 36523003, G11C 800

Patent

active

053717155

ABSTRACT:
A bit-line sensing control circuit includes a first circuit for activating a word line and a bit line associated with a first block of a memory cell array in response to a first initial activating clock. A delay circuit generates a second initial activating clock from the first initial activating clock a predetermined period after the first initial activation clock. A second circuit for activating a word line and a bit line associated with a second block of the memory cell array is initiated in response to the second initial activating clock. Because the second block of memory cells are sensed after the first block of memory cells, spike noise related problems are substantially avoided.

REFERENCES:
patent: 4739502 (1988-04-01), Nozaki

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