Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-06-15
2002-10-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S208000
Reexamination Certificate
active
06473325
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to semiconductor devices and, in particular, to a bit line sensing control circuit for a semiconductor memory device and a layout of the same.
2. Background Description
The chip size of a semiconductor memory device is one of the most important parameters regarding product competitiveness. Up to now, a significant amount of research has been undertaken and corresponding developments obtained to reduce a memory chip size, with a focus on fine line width and optimum circuit layout.
FIG. 1
is a circuit diagram illustrating a conventional bit line sensing control circuit. The bit line sensing control circuit includes equalizer circuits
10
and
20
, isolation circuits
12
and
22
, sense amplifier circuits
14
and
24
, a column select line (CSL) gate
16
, and power switching circuits
18
and
28
.
The equalizer circuits
10
and
20
serve to pre-charge bit lines to a VDD/2 level when a cell connected to the bit line is non-activated. This is to enable cell data “0” and “1” to have the same charge distribution margin when the cell is later activated, and then the bit lines are charge-distributed by the cell data.
The isolation circuits
12
and
22
connect the bit line sensing control circuit with selected memory cell array blocks and isolate the bit line sensing control circuit from non-selected memory cell array blocks when the bit line sensing control is connected with a plurality of memory cell array blocks, so as to minimize a load of a bit line during a bit line sensing operation.
The sense amplifier circuits
14
and
24
typically include N/P MOS type sense amplifier pairs and have a symmetrical configuration to maximize, for example, read and write characteristics of a memory chip. The sense amplifier circuits
14
and
24
amplify bit line data of tens to hundreds of millivolts (mV) that are charge-distributed to a CMOS level.
The CSL gate
16
is a gate that switches a bit line and an I/O line. The CSL gate
16
transfers data from a sensed bit line to a data line and transfers input data from an outside of a memory chip to a bit line. Also, the CSL gate
16
is a key component that decides read and write characteristics of a memory chip.
The power switching circuits
18
and
28
supply an electrical power to the sense amplifier circuits
14
and
24
, respectively.
FIG. 2
is a plan layout view illustrating a layout structure of the conventional bit line sensing control circuit of FIG.
1
. The equalizer circuits
10
and
20
are respectively located opposite end portions of the bit line sensing control circuit adjacent to the memory cell array. The isolation circuits
12
and
22
are located adjacent to the equalizer circuits
10
and
20
so that the bit line sensing control circuit may be connected with just selected memory cell array blocks. The CSL gate
16
is located on a central portion of the bit line sensing control circuit. Centered with respect to the CSL gate
16
, the N/P MOS type sense amplifier circuits
14
and
24
and the power switching circuits
18
and
28
are symmetrically arranged.
In sensing the cell data, the most important components of the bit line sensing control circuits are the N/P MOS type sense amplifiers
14
and
24
and the power switching circuits
18
and
28
. A stable and smooth sensing operation depends on the layout of these two types of circuits. Therefore, the layout of the N/P MOS sense amplifier circuits
14
and
24
has been designed in consideration of a load (e.g., a resistance) mismatch of a bit line and a bit line bar.
However, with respect to the power switching circuits, for example, in the case of a conventional lump type power switching circuit as shown in
FIG. 3
, a problem may occur in that a sufficient amount of a power may not be supplied at an appropriate time(s), according to a position of the sense amplifier. Also, in the case of a conventional distribute type power switching circuit as shown in
FIG. 4
, since the power switching circuit and the sense amplifier are connected with each other by a contact, a contact resistance may vary according to a manufacturing process. Therefore, it becomes very difficult to secure a stable and smooth sensing operation.
For at least the foregoing reasons, there is a need for a bit line sensing control circuit for a semiconductor memory device and a layout of the same, whereby the circuit and layout provide a stable and smooth sensing operation.
SUMMARY OF THE INVENTION
The problems stated above, as well as other related problems of the prior art, are solved by the present invention, a bit line sensing control circuit and a bit line sensing control circuit layout for a semiconductor memory device.
Advantageously, the bit line sensing control circuit (and layout) according to the present invention provides a smooth, stable, and high speed sensing operation. By arranging a power transistor inside a sense amplifier to have a sufficient capacity, the sensing speed of the bit line sensing control circuit can be improved. Also, since the power transistor is arranged inside the sense amplifier, the layout area of the bit line sensing control circuit can be reduced, and a layout efficiency of the bit line sensing control circuit can be improved. Moreover, since a load mismatch between an NMOS sense amplifier and a column sense transistor is prevented, an initial sensing operation becomes stable and smooth.
According to an aspect of the present invention, there is provided a layout of a bit line sensing control circuit for a semiconductor memory device. The layout includes two bit line pairs extending in a first direction. A power contact is arranged between the two bit line pairs. A power gate is arranged around the power contact. A plurality of sense transistors respectively have a plurality of sense transistor gates. The plurality of sense transistor gates are arranged around the power gate. A pair of control line contacts is arranged in a second direction at an adjacent location outside the two bit line pairs. A control line extends in the second direction and is connected to the power gate through the pair of control line contacts. A power line extends in the second direction adjacent to the control line and, is connected to an active area surrounded by the power gate through the power contact.
According to another aspect of the present invention, opposite sides of the power line and the control line respectively form a convex shape and a concave shape.
According to yet another aspect of the present invention, the plurality of sense transistors are PMOS transistors, and the plurality of gates of the PMOS transistors have a letter “L” shape.
According to still yet another aspect of the present invention, the plurality of sense transistors are NMOS transistors, and the plurality of gates of the NMOS transistors have a letter “D” shape.
According to an additional aspect of the present invention, there is provided a bit line sensing control circuit for a semiconductor memory device. The bit line sensing control circuit includes first and second bit line pairs extending in a first direction. Each of the pairs have first and second bit lines. A power contact is arranged between the first and second bit line pairs. A power gate is arranged around the power contact. A first sense transistor is arranged adjacent to an upper-left side of the power gate. The first sense transistor has a gate connected to the first bit line of the first bit line pair, a drain connected to the second bit line of the first bit line pair and a source connected to the power contact through the power gate. A second sense transistor is arranged adjacent to an upper-right side of the power gate. The second sense transistor has a gate connected to the second bit line of the first bit line pair, a drain connected to the first bit line of the first bit line pair and a source connected to the power contact through the power gate. A third sense transistor is arranged adjacent to a lower-left side of the power gate. The third sense tr
Joo Jae-Hoon
Kang Sang-Suk
Lee Jong-Eon
Lee Yun-Sang
Auduong Gene N.
F. Chau & Associates LLP
Nelms David
Samsung Electronics Co,. Ltd.
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