Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-03-07
2001-05-29
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S149000, C365S191000, C365S203000
Reexamination Certificate
active
06240026
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a circuit and method for triggering control circuitry in a memory device, and particularly to a sense circuit and method for enabling boost circuitry of the memory device based upon the activity of sense amplifiers thereof.
2. Background of the Invention
Today's dynamic random access memory (DRAM) devices typically include at least one memory cell array organized in rows and columns of capacitive-storage memory cells, with each row of memory cells being connected to a distinct word line and each column of memory cells being connected to a distinct bit line. Address decode circuitry is included to select a word line based upon the value of the address provided to the DRAM device. A distinct sense amplifier is connected to each pair of bit lines and amplifies the differential voltage placed thereon from accessing a row of memory cells.
In executing a memory access operation, such as a read, write or refresh operation, a word line is selected and driven to the power supply voltage value, Vdd, so that the contents of the memory cells in the selected row of memory cells are placed upon the bit lines of the DRAM device. When the sense amplifiers are powered up and connected to the bit lines, boost circuitry is enabled to capacitively boost the selected word line to a boosted voltage in excess of the power supply voltage value. With the voltage on the selected word line being at the boosted voltage, a charge corresponding to the power supply voltage may be capacitively stored in a memory cell in the selected row to refresh the contents of the memory cell. Storing a charge corresponding to the power supply voltage, as opposed to a charge corresponding to a lesser voltage value as would occur without boost circuitry, advantageously lengthens the amount of time until the capacitive memory cell needs to be refreshed.
During a memory access operation, any line that can capacitively couple to the selected word line can conceivably change the voltage and/or charge appearing thereon. This may undesirably alter the value of the boosted voltage to which the selected word line is to be later capacitively boosted.
Sense amplifiers are typically powered up and/or connected to high reference voltage level Vdd and low reference voltage level Vss during a memory access operation and particularly immediately following the selected row of memory cells being connected to the bit lines. Because the number of sense amplifiers that are simultaneously powered up and/or turned on may exceed one thousand, an appreciable amount of noise, in the form of a voltage spike or pulse, is typically generated by powering the sense amplifiers. The extent of the noise generated from powering the sense amplifiers has been seen to substantially effect the ability of the boost circuitry to boost the voltage appearing on the selected word line to the desired voltage level.
Based upon the foregoing, there is a need for a circuit and method for reducing the effects of noise on the operation of a DRAM device and particularly the operation of the boost circuitry thereof.
SUMMARY OF THE INVENTION
The present invention overcomes the shortcomings in prior DRAM devices and satisfies a significant need for a DRAM device which substantially reduces the amount of noise in boosting word lines of a DRAM device during a memory access operation. The DRAM device includes an array of memory cells arranged in a plurality of rows and columns of memory cells, with each row of memory cells being coupled to a distinct word line and each column of memory cells being coupled to a distinct bit line. A sense amplifier is coupled to each bit line pair for sensing a voltage differential appearing across the bit line pair (due to providing the contents from the memory cells in a selected row on the bit lines) and driving the bit lines towards reference levels Vss and Vdd accordingly. Equilibration circuitry precharges and equalizes the voltages across the bit lines of each bit line pair to an intermediate voltage level.
The DRAM device further includes a boost circuit for boosting a voltage appearing on a selected word line to a boosted voltage outside of the power supply range. The present DRAM device further includes a sense circuit connected to a bit line that is associated with a column of unused memory cells, such as memory cells appearing along the border of the memory cell array. The sense circuit triggers or enables the boost circuit to drive the selected word line to the boosted voltage after the sense amplifiers have finished detecting the voltage differential across each bit line pair. The self-timed sense circuit enables the boost circuit upon a voltage appearing on the associated bit line crossing a predetermined voltage level.
During a memory access operation, such as a memory read, write or refresh operation, the bit lines are initially precharged and equalized at the intermediate voltage level by the equilibration circuitry. The addressed or selected word line is then driven to a voltage level to connect the selected row of memory cells to the bit lines. At this point, the contents of the selected row of memory cells are placed on the bit lines so as to cause a voltage differential between the bit lines of each bit line pair. The sense amplifiers are then powered or enabled and sense the voltage differential appearing across the bit lines of each bit line pair and accordingly drive the bit lines towards the reference voltage levels, Vss and Vdd. As the voltage appearing on the bit line to which the sense circuit is connected crosses the predetermined voltage level, such as a voltage level between the intermediate voltage level and high reference voltage Vdd, the sense circuit asserts a signal to enable the boost circuit. The predetermined voltage level is a voltage level that ensures that a period of time has elapsed from the time the sense amplifiers are initially powered so that noise generated thereby is no longer present. The enabled boost circuit boosts the voltage level of the selected word line beyond a reference voltage level, such as to a voltage level greater than Vdd, so that a memory cell in the selected row is capable of storing a charge associated with either reference voltage level, Vss or Vdd, therein. By waiting a period of time following the sense amplifiers being initially powered to boost the selected word line, the selected word line is boosted to the desired boosted voltage level.
REFERENCES:
patent: 5510749 (1996-04-01), Arimoto
patent: 6009023 (1999-12-01), Lu et al.
patent: 6018177 (2000-01-01), Chi
Guritz Elmer Henry
Laurent Duane Giles
Worley James Leon
Galanthay Theodore E.
Ho Hoai V.
Jorgenson Lisa K.
Nelms David
STMicroelectronics Inc.
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