Bit line sense-amplifier for a semiconductor memory device...

Details Bit line sense-amplifier for a semiconductor memory device... Bit line sense-amplifier for a semiconductor memory device...

1999-12-21

2001-08-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S203000

Reexamination Certificate

active

06272059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a bit line sense-amplifier for a semiconductor memory device more particularly to a method for driving a bit line sense-amplifier for a semiconductor memory device which does not apply a bit line precharge voltage by using a switching means in an equalization operation, performs an equalization operation by interconnecting sense-amplifier lines, then performs a precharge operation by applying a bit line precharge voltage through NMOS transistor of the switching means, increases a sensing speed by reducing a loading of a sense-amplifier, decreases a transient current, and minimizes a power-consumption by performing a precharge operation after a bit line equalization.
2. Description of the Prior Art
FIG. 1
is a circuit diagram of a conventional bit line sense-amplifier.
Referring to
FIG. 1
, the conventional bit line sense-amplifier as of a folded bit line structure includes: a unit cell
1
which is connected between a first bit line BITH and a cell plate voltage terminal VCP, and is comprised of a first NMOS. transistor MN
1
and a cell capacitance C
1
; a first line connector
2
which is comprised of second and third. NMOS transistors (MN
2
, MN
3
), and achieves a connection or a cut-off between first bit lines (BITH, /BITH) and sense-amplifier lines (SA, /SA) by using a first bit line cut-off signal BISH; a second line connector
3
which is comprised of 10th and 11th NMOS transistors (MN
10
, MN
11
), and achieves a connection or a cut-off between second bit lines (BITL, /BITL) and sense-amplifier lines (SA , /SA) by using a second bit line cut-off signal BISL; a sense-amplifier
5
which is comprised of first and second PMOS transistors (MP
1
, MP
2
) and 8th and 9th NMOS transistors (MN
8
, MN
9
), is connected sense-amplifier lines (SA, /SA), is driven by sense-amplifier control signals (RTO, /S), and performs a bit line sensing operation; and a data bus line connector
6
which is comprised of 12th and 13th NMOS transistors (MN
12
, MN
13
), is operated by a column selection signal YI_SEL, and achieves a connection or a cut-off between sense-amplifier lines (SA, /SA) and data bus lines (DB, /DB).
A bit line sensing operation of the conventional bit line sense-amplifier shown in
FIG. 1
will be described with reference to
FIGS. 2-3
.
FIG. 2
is a circuit diagram showing a driving method of the conventional bit line sense-amplifier shown in
FIG. 1
, and
FIG. 3
is a timing diagram of the conventional bit line sense-amplifier shown in FIG.
1
.
As to a bit line sense-amplifier in an initial state as shown in FIG.
2
(
a
), since the first and second bit line cut-off signals (BISH, BISL) are at a high level state as shown in FIGS.
3
(
a
)-
3
(
b
), the first and second bit lines (BITH, /BITH, BITL, /BITL) are connected to the sense-amplifier lines (SA, /SA). Also, a bit line precharge voltage VBLP being a half Vcc power generator is applied to the above lines as shown in FIGS.
3
(
c
),
3
(
h
) and
3
(
i
).
Then, as shown in FIG.
2
(
b
), the second bit lines (BITL, /BITL) are isolated from the sense-amplifier lines (SA, /SA) by the second bit line cut-off signal BISL.
That is, as shown in FIGS.
3
(
b
)-
3
(
c
), if the second bit line cut-off signal BISL and a bit line equalization signal BLP are changed from a high level state to a low level state, the fifth, sixth and seventh NMOS transistors (MN
5
, MN
6
, MN
7
) comprising a bit line equalization unit
4
and the 10th and 11th NMOS transistors (MN
10
, MN
11
) comprising the second line connector
3
, thereby separating the second bit lines (BITL, /BITL) from the sense-amplifier lines (SA, /SA).
Then, a word line WL is selected as shown in FIG.
3
(
d
), a voltage division occurs in the first bit line BITH shown in FIG.
2
(
c
) and the sense-amplifier line SA shown in FIGS.
3
(
h
) and
3
(
i
).
After that, a sensing operation and a write-back operation to a storage node STR inside of the unit cell
1
are performed in the sense-amplifier
5
.
That is, sense-amplifier control signals (RTO, /S) are applied as shown in FIGS.
3
(
f
) and
3
(
g
) so that an amplified signal is applied to the sense-amplifier lines (SA, /SA). As shown in FIG.
2
(
d
), the amplified signal is write-back processed to a storage node inside of the unit cell
1
.
In this course, the sense-amplifier lines (SA, /SA) and the first bit lines (BITH, /BITH) are interconnected so that a power-consumption occurs according to a loading of the first bit lines (BITH, /BITH). Here, the second and third NMOS transistors comprising the first line connector
2
are turned on because the first bit line cut-off signal BISH is at a high level state, so that the upper bit line is connected to the sense-amplifier lines.
Then, an equalization operation and a precharge operation of the first and second bit lines (BITH, /BITH, BITL, /BITL) and the sense-amplifier lines (SA, /SA) are performed at the same time.
Namely, as shown in FIGS.
3
(
d
),
3
(
f
) and
3
(
g
), a word line WL is changed from a high level state to a low level state, and the sense-amplifier control signals (RTO, /S) are disabled with a half Vcc level. As shown in FIGS.
3
(
b
) and
3
(
c
), the second bit line cut-off signal BISL and a bit line equalization signal BLP are changed from a low level state to a high level state, so that the signals BISL and BLP are enabled. As shown in FIG.
2
(
e
), the first and second bit lines (BITH, /BITH, BITL, /BITL) and the sense-amplifier lines (SA, /SA) are equalized and precharged.
In this course, since the equalization operation and the precharge operation are performed at the same time, a voltage of one sense-amplifier line SA between two sense-amplifier lines (SA, /SA) is amplified as a first Vcc voltage as shown in FIG.
3
(
h
) by a sensing operation, and a voltage of the other sense-amplifier line (/SA) drops to a ground level voltage Vss, thereby occurring a power-consumption in a precharging process.
Accordingly, unnecessary power-consumption generated in a conventional sensing and precharging process should be removed, and increasing a sensing speed should minimize a current consumption in a chip operation.
To solve this problem, there is provided three kinds of methods in the present invention.
SUMMARY OF THE INVENTION
Accordingly, the present invention is that directed to a bit line sense-amplifier for a semiconductor memory device and a method for driving the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
It is an objective of the present invention to provide a it line sense-amplifier for a semiconductor memory device and a method for driving the same, which prevent a power-consumption by performing a precharge operation after an equalization operation in a precharge operation.
To achieve the above objective, a bit line sense-amplifier for a semiconductor memory device includes: first and second bit lines respectively having two bit lines, for transmitting a stored data to a memory cell; sense-amplifier lines for transmitting a data loaded on the first bit line to a sense-amplifier; first and second switches which are controlled by first and second control signals, and selectively connect two bit lines of the first bit line to the sense-amplifier lines; third and fourth switches which are controlled by third and fourth control signals, and selectively connect two bit lines of the second bit line to the sense-amplifier lines; and a fifth switch which is controlled by a fifth control signal, and selectively applies a bit line precharge voltage to the sense-amplifier lines.
A method for driving a bit line sense-amplifier includes the steps of: (a) interconnecting first and second bit lines and sense-amplifier lines, and applying a bit line precharge voltage to the sense-amplifier lines; (b) separating the second bit line from the sense-amplifier lines, and separating the sense-amplifier lines from the bit line precharge voltage; (c) selecting a desired memory cell, and trans

Affiliated with

Also associated with

Rating

Bit line sense-amplifier for a semiconductor memory device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bit line sense-amplifier for a semiconductor memory device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bit line sense-amplifier for a semiconductor memory device... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2494544