Bit line sense amplifier driving control circuits and...

Details Bit line sense amplifier driving control circuits and... Bit line sense amplifier driving control circuits and...

2003-03-14

2004-09-21

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030, C365S207000, C365S194000

Reexamination Certificate

active

06795372

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2002-55001, filed Sep. 11, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
The present invention relates to synchronous Dynamic Random Access Memories (DRAM), and more particularly, to a bit line sense amplifier driving control circuits and methods for synchronous DRAMs.
BACKGROUND OF THE INVENTION
Clocked DRAMs, also referred to as synchronous DRAMs, are widely used integrated circuit memory devices. According to a general data accessing method for a synchronous DRAM, a row address and a column address are sequentially input to a memory cell array with a time interval therebetween, to read or write data from or to the memory cell. The time interval from the row address input to the column address input should be long enough to allow correct recognition of the input row address so that valid data can be retrieved from the memory cell.
Since the synchronous DRAM operates in synchronization with a clock, a point of time when the row address or the column address is input is determined according to the clock cycle. A shorter clock cycle may speed up the synchronous DRAM, but may allow a shorter time lapse between the row address input and the column address input, and thus it may lead to an erroneous recognition of the row address.
FIG. 1
is a circuit diagram showing an example of a conventional bit line sense amplifier driving control circuit for a synchronous DRAM. Referring to
FIG. 1
, the conventional bit line sense amplifier driving control circuit includes a bit line sense amplifier controller
10
and a bit line sense amplifier driver
20
.
The bit line sense amplifier controller
10
includes a first control circuit
11
and a second control circuit
12
. The first control circuit
11
outputs an N sense amplifier control signal NSA_CTL for providing a first operating voltage to the NMOS transistors (not shown) of a bit line sense amplifier. The second control circuit
12
outputs a P sense amplifier control signal PSA_CTL for providing a second operating voltage to the PMOS transistors (not shown) of the bit line sense amplifier.
The first control circuit
11
includes a NAND gate
13
and an inverter
14
. The NAND gate
13
performs a NAND-operation on a sensing start signal SA_SE_ST of the bit line sense amplifier and a row block information signal RA according to a row address input to output a predetermined control signal CTL. The inverter
14
inverts the control signal CTL to output the N sense amplifier control signal NSA_CTL.
The second control circuit
12
includes a first inverter
15
and a second inverter
16
. The first inverter
15
inverts the control signal CTL. The second inverter
16
inverts an output signal of the first inverter
15
to output the P sense amplifier control signal PSA_CTL.
The bit line sense amplifier driver
20
is arranged in a column direction along a plurality of memory cell arrays
30
. The bit line sense amplifier driver
20
includes a P sense amplifier driver circuit
21
and an N sense amplifier driver circuit
22
. The P sense amplifier driver circuit
21
is a circuit to provide the second operating voltage to the PMOS transistors of the bit line sense amplifier. The N sense amplifier driver circuit
22
is a circuit to provide the first operating voltage to the NMOS transistors of the bit line sense amplifier.
The P sense amplifier driver circuit
21
includes a plurality of PMOS transistors
23
and the N sense amplifier driver circuit
22
includes a plurality of NMOS transistors
24
. Each drain of the PMOS transistors
23
is connected to a local array line LA, and each source of the PMOS transistors
23
is connected to an internal voltage VCC. Each gate of the PMOS transistors
23
receives the P sense amplifier control signal PSA_CTL. As the plurality of PMOS transistors
23
are turned on by the P sense amplifier control signal PSA_CTL, the local array line LA transitions to a voltage level equal to the internal voltage VCC.
Each drain of the NMOS transistors
24
is connected to a local array bar line LAB, and each source of the NMOS transistors
24
is connected to ground. Each gate of the NMOS transistors
24
receives the N sense amplifier control signal NSA_CTL. As the plurality of NMOS transistor
24
is turned on by the N sense amplifier control signal NSA_CTL, the local array bar line LAB transitions to a ground voltage level.
The operation of the conventional bit line sense amplifier driving control circuit having the above-described configuration will be described with reference to FIG.
2
.
FIG. 2
is a timing diagram of input/output signals involved in the bit line sense amplifier driving control circuit shown in FIG.
1
. Referring to
FIG. 2
, when a control command ACTIVE is input in synchronization with a clock signal CLK and a row address is input, the row block information signal RA is enabled to activate a corresponding word line WL.
When the word line WL is activated, cell transistors in the memory cell arrays
30
connected to the word line WL are turned on, and data stored in cell capacitors are transmitted to bit lines. At this time, since the cell capacitors share charges with the bit lines, the initial voltage (reference voltage) level of the bit lines before the data are received is slightly changed into data voltage.
When the bit line sense amplifier sensing start signal SA_SE_ST is enabled, the P and N amplifier control signals PSA_CTL and NSA_CM are enabled to turn on the PMOS and NMOS transistors
23
and
24
. As discussed above with reference to
FIG. 1
, and as shown in
FIG. 2
, as the plurality of PMOS transistors
23
and the plurality of NMOS tansistors
24
are turned on by the respective signals PSA_CTL and NSA-CLT, the local array line LA and the local array bar line LAB transition to VCC and ground voltage, respectively. When the PMOS ants NMOS transistors
23
and
24
are turned on, first and second operating voltages are applied to the bit line sense amplifier, and the data voltage of the bit line is primarily amplified by the bit line sense amplifiers.
When a read command READ and a column address are input, a column select signal CSL is generated, the data voltage of the bit line is secondarily amplified while passing through a column path, and the amplified data is output as a data signal. As such, when the column select signal CSL is enabled, gate transistors of a data bus that has a particular column address on the activated word line are turned on, and the primarily amplified data are transmitted to the data bus.
The primary data amplification following the row address input and before the column address input needs to be performed for a sufficient amount of time to a valid level in order to retrieve valid data. If a column address is input too early without sufficient primary data amplification, invalid data may be amplified during the secondary amplification in the column path, so that incorrect data is retrieved.
Referring to
FIG. 2
, when the primary data amplification in the bit lines BL and /BL ends too early, i.e., in an invalid period, the data is invalid. When the primary data amplification in the bit lines BL and /BL is done for a sufficient period of time, i.e., up to a valid period, the data is valid. In other words, only when a column address is input in the valid period, valid data can be retrieved.
However, with the recent desire for semiconductor memory devices operating at higher frequency in order to enhance system's performance, the clock cycle in synchronous semiconductor memory devices may become shorter. Accordingly, the time period allowed until a column address is input after the input of a row address may become shorter. Therefore, the column address may be input without primary data amplification for a sufficient duration so that a column select signal CSL is generated in the invalid period, as shown in
FIG. 2
, and thus invalid data may be retrieved.

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