Bit line sense amplifier array for semiconductor memory device

Details Bit line sense amplifier array for semiconductor memory device Bit line sense amplifier array for semiconductor memory device

1996-10-09

1998-06-16

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

36518911, G11C 706

Patent

active

057682011

ABSTRACT:
A bit line sense amplifier array for a semiconductor memory device which has a memory cell array with at least two memory cells sharing a metal strapping region, and a plurality of true and complementary bit lines for transferring data from the at least two memory cells externally or transferring external data to the at least two memory cells. The bit line sense amplifier array comprises at least one sense amplifier block for sensing and amplifying data on the true and complementary bit lines. The sense amplifier block includes first and second sense amplifier array for sensing and amplifying the data on the true and complementary bit lines, respectively, a first bias circuit for applying a first voltage to the first and second sense amplifier array, a second bias circuit for applying a second voltage to the first and second sense amplifier array, a pair of pull-up drivers for generating a restore signal in response to a global restore control signal to drive the first bias circuit, a pair of pull-down drivers for generating a sensing signal in response to a global sensing control signal to drive the second bias circuit, and an equalizer for precharging the true and complementary bit lines with half the first voltage and equalizing voltages supplied to the true and complementary bit lines.

REFERENCES:
patent: 4511997 (1985-04-01), Nozaki et al.
patent: 4546457 (1985-10-01), Nozaki et al.
patent: 5406526 (1995-04-01), Sugibayashi et al.
patent: 5544105 (1996-08-01), Hirose et al.

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